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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt < %s -passes='sroa<preserve-cfg>' -S | FileCheck %s --check-prefixes=CHECK,CHECK-PRESERVE-CFG3; RUN: opt < %s -passes='sroa<modify-cfg>' -S | FileCheck %s --check-prefixes=CHECK,CHECK-MODIFY-CFG4 5target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n8:16:32:64"6 7; This test checks that SROA runs mem2reg on scalable vectors.8 9define <vscale x 16 x i1> @alloca_nxv16i1(<vscale x 16 x i1> %pg) vscale_range(1) {10; CHECK-LABEL: @alloca_nxv16i1(11; CHECK-NEXT: ret <vscale x 16 x i1> [[PG:%.*]]12;13 %pg.addr = alloca <vscale x 16 x i1>14 store <vscale x 16 x i1> %pg, ptr %pg.addr15 %1 = load <vscale x 16 x i1>, ptr %pg.addr16 ret <vscale x 16 x i1> %117}18 19define <vscale x 16 x i8> @alloca_nxv16i8(<vscale x 16 x i8> %vec) vscale_range(1) {20; CHECK-LABEL: @alloca_nxv16i8(21; CHECK-NEXT: ret <vscale x 16 x i8> [[VEC:%.*]]22;23 %vec.addr = alloca <vscale x 16 x i8>24 store <vscale x 16 x i8> %vec, ptr %vec.addr25 %1 = load <vscale x 16 x i8>, ptr %vec.addr26 ret <vscale x 16 x i8> %127}28 29; Test scalable alloca that can't be promoted. Mem2Reg only considers30; non-volatile loads and stores for promotion.31define <vscale x 16 x i8> @unpromotable_alloca(<vscale x 16 x i8> %vec) vscale_range(1) {32; CHECK-LABEL: @unpromotable_alloca(33; CHECK-NEXT: [[VEC_ADDR:%.*]] = alloca <vscale x 16 x i8>, align 1634; CHECK-NEXT: store volatile <vscale x 16 x i8> [[VEC:%.*]], ptr [[VEC_ADDR]], align 1635; CHECK-NEXT: [[TMP1:%.*]] = load volatile <vscale x 16 x i8>, ptr [[VEC_ADDR]], align 1636; CHECK-NEXT: ret <vscale x 16 x i8> [[TMP1]]37;38 %vec.addr = alloca <vscale x 16 x i8>39 store volatile <vscale x 16 x i8> %vec, ptr %vec.addr40 %1 = load volatile <vscale x 16 x i8>, ptr %vec.addr41 ret <vscale x 16 x i8> %142}43 44; Test we bail out when using an alloca of a fixed-length vector (VLS) that was45; bitcasted to a scalable vector.46define <vscale x 4 x i32> @cast_alloca_to_svint32_t(<vscale x 4 x i32> %type.coerce) vscale_range(1) {47; CHECK-LABEL: @cast_alloca_to_svint32_t(48; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i32> @llvm.vector.extract.v4i32.nxv4i32(<vscale x 4 x i32> [[TYPE_COERCE:%.*]], i64 0)49; CHECK-NEXT: [[TYPE_0_VEC_EXPAND:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>50; CHECK-NEXT: [[TYPE_0_VECBLEND:%.*]] = select <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>, <16 x i32> [[TYPE_0_VEC_EXPAND]], <16 x i32> undef51; CHECK-NEXT: [[TYPE_ADDR_0_VEC_EXTRACT:%.*]] = shufflevector <16 x i32> [[TYPE_0_VECBLEND]], <16 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>52; CHECK-NEXT: [[TMP2:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> poison, <4 x i32> [[TYPE_ADDR_0_VEC_EXTRACT]], i64 0)53; CHECK-NEXT: ret <vscale x 4 x i32> [[TMP2]]54;55 %type = alloca <16 x i32>56 %type.addr = alloca <16 x i32>57 store <vscale x 4 x i32> %type.coerce, ptr %type58 %type1 = load <16 x i32>, ptr %type59 store <16 x i32> %type1, ptr %type.addr60 %1 = load <16 x i32>, ptr %type.addr61 %2 = load <vscale x 4 x i32>, ptr %type.addr62 ret <vscale x 4 x i32> %263}64 65; When casting from VLA to VLS via memory check we bail out when producing a66; GEP where the element type is a scalable vector.67define <vscale x 4 x i32> @cast_alloca_from_svint32_t() vscale_range(1) {68; CHECK-LABEL: @cast_alloca_from_svint32_t(69; CHECK-NEXT: [[RETVAL_COERCE:%.*]] = alloca <vscale x 4 x i32>, align 1670; CHECK-NEXT: store <16 x i32> zeroinitializer, ptr [[RETVAL_COERCE]], align 1671; CHECK-NEXT: [[TMP1:%.*]] = load <vscale x 4 x i32>, ptr [[RETVAL_COERCE]], align 1672; CHECK-NEXT: ret <vscale x 4 x i32> [[TMP1]]73;74 %retval = alloca <16 x i32>75 store <16 x i32> zeroinitializer, ptr %retval76 %retval.coerce = alloca <vscale x 4 x i32>77 call void @llvm.memcpy.p0.p0.i64(ptr align 16 %retval.coerce, ptr align 16 %retval, i64 64, i1 false)78 %1 = load <vscale x 4 x i32>, ptr %retval.coerce79 ret <vscale x 4 x i32> %180}81 82; Test we bail out when using an alloca of a fixed-length vector (VLS) that was83; bitcasted to a scalable vector.84define void @select_load_alloca_to_svdouble_t() vscale_range(1) {85; CHECK-LABEL: @select_load_alloca_to_svdouble_t(86; CHECK-NEXT: [[Z:%.*]] = alloca <16 x half>, align 3287; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 0, 088; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], ptr [[Z]], ptr null89; CHECK-NEXT: [[VAL:%.*]] = load <vscale x 2 x double>, ptr [[COND]], align 1690; CHECK-NEXT: ret void91;92 %z = alloca <16 x half>93 %cmp = icmp eq i32 0, 094 %cond = select i1 %cmp, ptr %z, ptr null95 %val = load <vscale x 2 x double>, ptr %cond, align 1696 ret void97}98 99define void @select_store_alloca_to_svdouble_t(<vscale x 2 x double> %val) vscale_range(1) {100; CHECK-LABEL: @select_store_alloca_to_svdouble_t(101; CHECK-NEXT: [[Z:%.*]] = alloca <16 x half>, align 32102; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 0, 0103; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], ptr [[Z]], ptr null104; CHECK-NEXT: store <vscale x 2 x double> [[VAL:%.*]], ptr [[COND]], align 16105; CHECK-NEXT: ret void106;107 %z = alloca <16 x half>108 %cmp = icmp eq i32 0, 0109 %cond = select i1 %cmp, ptr %z, ptr null110 store <vscale x 2 x double> %val, ptr %cond, align 16111 ret void112}113 114define <4 x i32> @fixed_alloca_fixed_from_scalable(<vscale x 4 x i32> %a) vscale_range(1) {115; CHECK-LABEL: @fixed_alloca_fixed_from_scalable(116; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i32> @llvm.vector.extract.v4i32.nxv4i32(<vscale x 4 x i32> [[A:%.*]], i64 0)117; CHECK-NEXT: ret <4 x i32> [[TMP1]]118;119 %tmp = alloca <4 x i32>120 store <vscale x 4 x i32> %a, ptr %tmp121 %cast = load <4 x i32>, ptr %tmp122 ret <4 x i32> %cast123}124 125define <2 x i8> @fixed_alloca_fixed_from_scalable_requires_bitcast(<vscale x 16 x i1> %a) vscale_range(1) {126; CHECK-LABEL: @fixed_alloca_fixed_from_scalable_requires_bitcast(127; CHECK-NEXT: [[TMP1:%.*]] = bitcast <vscale x 16 x i1> [[A:%.*]] to <vscale x 2 x i8>128; CHECK-NEXT: [[TMP2:%.*]] = call <2 x i8> @llvm.vector.extract.v2i8.nxv2i8(<vscale x 2 x i8> [[TMP1]], i64 0)129; CHECK-NEXT: ret <2 x i8> [[TMP2]]130;131 %tmp = alloca <2 x i8>132 store <vscale x 16 x i1> %a, ptr %tmp133 %cast = load <2 x i8>, ptr %tmp134 ret <2 x i8> %cast135}136 137define <2 x ptr> @fixed_alloca_fixed_from_scalable_inttoptr(<vscale x 4 x i32> %a) vscale_range(1) {138; CHECK-LABEL: @fixed_alloca_fixed_from_scalable_inttoptr(139; CHECK-NEXT: [[TMP1:%.*]] = bitcast <vscale x 4 x i32> [[A:%.*]] to <vscale x 2 x i64>140; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i64> @llvm.vector.extract.v2i64.nxv2i64(<vscale x 2 x i64> [[TMP1]], i64 0)141; CHECK-NEXT: [[TMP2:%.*]] = inttoptr <2 x i64> [[TMP3]] to <2 x ptr>142; CHECK-NEXT: ret <2 x ptr> [[TMP2]]143;144 %tmp = alloca <4 x i32>145 store <vscale x 4 x i32> %a, ptr %tmp146 %cast = load <2 x ptr>, ptr %tmp147 ret <2 x ptr> %cast148}149 150define <4 x i32> @fixed_alloca_fixed_from_scalable_ptrtoint(<vscale x 2 x ptr> %a) vscale_range(1) {151; CHECK-LABEL: @fixed_alloca_fixed_from_scalable_ptrtoint(152; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint <vscale x 2 x ptr> [[A:%.*]] to <vscale x 2 x i64>153; CHECK-NEXT: [[TMP2:%.*]] = bitcast <vscale x 2 x i64> [[TMP1]] to <vscale x 4 x i32>154; CHECK-NEXT: [[TMP_0_CAST:%.*]] = call <4 x i32> @llvm.vector.extract.v4i32.nxv4i32(<vscale x 4 x i32> [[TMP2]], i64 0)155; CHECK-NEXT: ret <4 x i32> [[TMP_0_CAST]]156;157 %tmp = alloca <4 x i32>158 store <vscale x 2 x ptr> %a, ptr %tmp159 %cast = load <4 x i32>, ptr %tmp160 ret <4 x i32> %cast161}162 163define <2 x ptr> @fixed_alloca_fixed_from_scalable_ptrtoptr(<vscale x 2 x ptr> %a) vscale_range(1) {164; CHECK-LABEL: @fixed_alloca_fixed_from_scalable_ptrtoptr(165; CHECK-NEXT: [[TMP_0_CAST:%.*]] = call <2 x ptr> @llvm.vector.extract.v2p0.nxv2p0(<vscale x 2 x ptr> [[A:%.*]], i64 0)166; CHECK-NEXT: ret <2 x ptr> [[TMP_0_CAST]]167;168 %tmp = alloca <2 x ptr>169 store <vscale x 2 x ptr> %a, ptr %tmp170 %cast = load <2 x ptr>, ptr %tmp171 ret <2 x ptr> %cast172}173 174define <2 x ptr> @fixed_alloca_fixed_from_scalable_ptrtoptr_different_addrspace(<vscale x 2 x ptr addrspace(1)> %a) vscale_range(1) {175; CHECK-LABEL: @fixed_alloca_fixed_from_scalable_ptrtoptr_different_addrspace(176; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint <vscale x 2 x ptr addrspace(1)> [[A:%.*]] to <vscale x 2 x i64>177; CHECK-NEXT: [[TMP2:%.*]] = call <2 x i64> @llvm.vector.extract.v2i64.nxv2i64(<vscale x 2 x i64> [[TMP1]], i64 0)178; CHECK-NEXT: [[TMP3:%.*]] = inttoptr <2 x i64> [[TMP2]] to <2 x ptr>179; CHECK-NEXT: ret <2 x ptr> [[TMP3]]180;181 %tmp = alloca <2 x ptr>182 store <vscale x 2 x ptr addrspace(1)> %a, ptr %tmp183 %cast = load <2 x ptr>, ptr %tmp184 ret <2 x ptr> %cast185}186 187define <vscale x 4 x i32> @fixed_alloca_scalable_from_fixed(<4 x i32> %a) vscale_range(1) {188; CHECK-LABEL: @fixed_alloca_scalable_from_fixed(189; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> poison, <4 x i32> [[A:%.*]], i64 0)190; CHECK-NEXT: ret <vscale x 4 x i32> [[TMP1]]191;192 %tmp = alloca <4 x i32>193 store <4 x i32> %a, ptr %tmp194 %cast = load <vscale x 4 x i32>, ptr %tmp195 ret <vscale x 4 x i32> %cast196}197 198define <vscale x 16 x i1> @fixed_alloca_scalable_from_fixed_requires_bitcast(<2 x i8> %a) vscale_range(1) {199; CHECK-LABEL: @fixed_alloca_scalable_from_fixed_requires_bitcast(200; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.v2i8(<vscale x 2 x i8> poison, <2 x i8> [[A:%.*]], i64 0)201; CHECK-NEXT: [[TMP2:%.*]] = bitcast <vscale x 2 x i8> [[TMP1]] to <vscale x 16 x i1>202; CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]203;204 %tmp = alloca <2 x i8>205 store <2 x i8> %a, ptr %tmp206 %cast = load <vscale x 16 x i1>, ptr %tmp207 ret <vscale x 16 x i1> %cast208}209 210define <vscale x 2 x ptr> @fixed_alloca_scalable_from_fixed_inttoptr(<4 x i32> %a) vscale_range(1) {211; CHECK-LABEL: @fixed_alloca_scalable_from_fixed_inttoptr(212; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> poison, <4 x i32> [[A:%.*]], i64 0)213; CHECK-NEXT: [[TMP2:%.*]] = bitcast <vscale x 4 x i32> [[TMP1]] to <vscale x 2 x i64>214; CHECK-NEXT: [[TMP_0_CAST:%.*]] = inttoptr <vscale x 2 x i64> [[TMP2]] to <vscale x 2 x ptr>215; CHECK-NEXT: ret <vscale x 2 x ptr> [[TMP_0_CAST]]216;217 %tmp = alloca <4 x i32>218 store <4 x i32> %a, ptr %tmp219 %cast = load <vscale x 2 x ptr>, ptr %tmp220 ret <vscale x 2 x ptr> %cast221}222 223define <vscale x 4 x i32> @fixed_alloca_scalable_from_fixed_ptrtoint(<2 x ptr> %a) vscale_range(1) {224; CHECK-LABEL: @fixed_alloca_scalable_from_fixed_ptrtoint(225; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint <2 x ptr> [[A:%.*]] to <2 x i64>226; CHECK-NEXT: [[TMP2:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> poison, <2 x i64> [[TMP1]], i64 0)227; CHECK-NEXT: [[TMP_0_CAST:%.*]] = bitcast <vscale x 2 x i64> [[TMP2]] to <vscale x 4 x i32>228; CHECK-NEXT: ret <vscale x 4 x i32> [[TMP_0_CAST]]229;230 %tmp = alloca <4 x i32>231 store <2 x ptr> %a, ptr %tmp232 %cast = load <vscale x 4 x i32>, ptr %tmp233 ret <vscale x 4 x i32> %cast234}235 236define <vscale x 2 x ptr> @fixed_alloca_scalable_from_fixed_ptrtoptr(<2 x ptr> %a) vscale_range(1) {237; CHECK-LABEL: @fixed_alloca_scalable_from_fixed_ptrtoptr(238; CHECK-NEXT: [[TMP_0_CAST:%.*]] = call <vscale x 2 x ptr> @llvm.vector.insert.nxv2p0.v2p0(<vscale x 2 x ptr> poison, <2 x ptr> [[A:%.*]], i64 0)239; CHECK-NEXT: ret <vscale x 2 x ptr> [[TMP_0_CAST]]240;241 %tmp = alloca <2 x ptr>242 store <2 x ptr> %a, ptr %tmp243 %cast = load <vscale x 2 x ptr>, ptr %tmp244 ret <vscale x 2 x ptr> %cast245}246 247define <vscale x 2 x ptr addrspace(1)> @fixed_alloca_scalable_from_fixed_ptrtoptr_different_addrspace(<2 x ptr> %a) vscale_range(1) {248; CHECK-LABEL: @fixed_alloca_scalable_from_fixed_ptrtoptr_different_addrspace(249; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint <2 x ptr> [[A:%.*]] to <2 x i64>250; CHECK-NEXT: [[TMP2:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> poison, <2 x i64> [[TMP1]], i64 0)251; CHECK-NEXT: [[TMP3:%.*]] = inttoptr <vscale x 2 x i64> [[TMP2]] to <vscale x 2 x ptr addrspace(1)>252; CHECK-NEXT: ret <vscale x 2 x ptr addrspace(1)> [[TMP3]]253;254 %tmp = alloca <2 x ptr>255 store <2 x ptr> %a, ptr %tmp256 %cast = load <vscale x 2 x ptr addrspace(1)>, ptr %tmp257 ret <vscale x 2 x ptr addrspace(1)> %cast258}259 260define <4 x i32> @scalable_alloca_fixed_from_scalable(<vscale x 4 x i32> %a) vscale_range(1) {261; CHECK-LABEL: @scalable_alloca_fixed_from_scalable(262; CHECK-NEXT: [[TMP:%.*]] = alloca <vscale x 4 x i32>, align 16263; CHECK-NEXT: store <vscale x 4 x i32> [[A:%.*]], ptr [[TMP]], align 16264; CHECK-NEXT: [[CAST:%.*]] = load <4 x i32>, ptr [[TMP]], align 16265; CHECK-NEXT: ret <4 x i32> [[CAST]]266;267 %tmp = alloca <vscale x 4 x i32>268 store <vscale x 4 x i32> %a, ptr %tmp269 %cast = load <4 x i32>, ptr %tmp270 ret <4 x i32> %cast271}272 273define <vscale x 4 x i32> @scalable_alloca_scalable_from_fixed(<4 x i32> %a) vscale_range(1) {274; CHECK-LABEL: @scalable_alloca_scalable_from_fixed(275; CHECK-NEXT: [[TMP:%.*]] = alloca <vscale x 4 x i32>, align 16276; CHECK-NEXT: store <4 x i32> [[A:%.*]], ptr [[TMP]], align 16277; CHECK-NEXT: [[CAST:%.*]] = load <vscale x 4 x i32>, ptr [[TMP]], align 16278; CHECK-NEXT: ret <vscale x 4 x i32> [[CAST]]279;280 %tmp = alloca <vscale x 4 x i32>281 store <4 x i32> %a, ptr %tmp282 %cast = load <vscale x 4 x i32>, ptr %tmp283 ret <vscale x 4 x i32> %cast284}285 286define i16 @scalar_alloca_scalar_from_scalable(<vscale x 16 x i1> %a) vscale_range(1) {287; CHECK-LABEL: @scalar_alloca_scalar_from_scalable(288; CHECK-NEXT: [[TMP:%.*]] = alloca i16, align 2289; CHECK-NEXT: store <vscale x 16 x i1> [[A:%.*]], ptr [[TMP]], align 2290; CHECK-NEXT: [[TMP_0_CAST:%.*]] = load i16, ptr [[TMP]], align 2291; CHECK-NEXT: ret i16 [[TMP_0_CAST]]292;293 %tmp = alloca i16294 store <vscale x 16 x i1> %a, ptr %tmp295 %cast = load i16, ptr %tmp296 ret i16 %cast297}298 299define <vscale x 16 x i1> @scalar_alloca_scalable_from_scalar(i16 %a) vscale_range(1) {300; CHECK-LABEL: @scalar_alloca_scalable_from_scalar(301; CHECK-NEXT: [[TMP:%.*]] = alloca i16, align 2302; CHECK-NEXT: store i16 [[A:%.*]], ptr [[TMP]], align 2303; CHECK-NEXT: [[TMP_0_CAST:%.*]] = load <vscale x 16 x i1>, ptr [[TMP]], align 2304; CHECK-NEXT: ret <vscale x 16 x i1> [[TMP_0_CAST]]305;306 %tmp = alloca i16307 store i16 %a, ptr %tmp308 %cast = load <vscale x 16 x i1>, ptr %tmp309 ret <vscale x 16 x i1> %cast310}311 312define { <2 x i32>, <2 x i32> } @fixed_struct_alloca_fixed_from_scalable(<vscale x 4 x i32> %a) vscale_range(1) {313; CHECK-LABEL: @fixed_struct_alloca_fixed_from_scalable(314; CHECK-NEXT: [[TMP:%.*]] = alloca { <2 x i32>, <2 x i32> }, align 8315; CHECK-NEXT: store <vscale x 4 x i32> [[A:%.*]], ptr [[TMP]], align 8316; CHECK-NEXT: [[TMP_0_CAST_FCA_0_LOAD:%.*]] = load <2 x i32>, ptr [[TMP]], align 8317; CHECK-NEXT: [[CAST_FCA_0_INSERT:%.*]] = insertvalue { <2 x i32>, <2 x i32> } poison, <2 x i32> [[TMP_0_CAST_FCA_0_LOAD]], 0318; CHECK-NEXT: [[TMP_8_CAST_FCA_1_GEP_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[TMP]], i64 8319; CHECK-NEXT: [[TMP_8_CAST_FCA_1_LOAD:%.*]] = load <2 x i32>, ptr [[TMP_8_CAST_FCA_1_GEP_SROA_IDX]], align 8320; CHECK-NEXT: [[CAST_FCA_1_INSERT:%.*]] = insertvalue { <2 x i32>, <2 x i32> } [[CAST_FCA_0_INSERT]], <2 x i32> [[TMP_8_CAST_FCA_1_LOAD]], 1321; CHECK-NEXT: ret { <2 x i32>, <2 x i32> } [[CAST_FCA_1_INSERT]]322;323 %tmp = alloca { <2 x i32>, <2 x i32> }324 store <vscale x 4 x i32> %a, ptr %tmp325 %cast = load { <2 x i32>, <2 x i32> }, ptr %tmp326 ret { <2 x i32>, <2 x i32> } %cast327}328 329define <vscale x 4 x i64> @fixed_struct_alloca_scalable_from_fixed({ <2 x ptr>, <2 x ptr> } %a) vscale_range(1) {330; CHECK-LABEL: @fixed_struct_alloca_scalable_from_fixed(331; CHECK-NEXT: [[TMP:%.*]] = alloca { <2 x ptr>, <2 x ptr> }, align 16332; CHECK-NEXT: [[A_FCA_0_EXTRACT:%.*]] = extractvalue { <2 x ptr>, <2 x ptr> } [[A:%.*]], 0333; CHECK-NEXT: store <2 x ptr> [[A_FCA_0_EXTRACT]], ptr [[TMP]], align 16334; CHECK-NEXT: [[A_FCA_1_EXTRACT:%.*]] = extractvalue { <2 x ptr>, <2 x ptr> } [[A]], 1335; CHECK-NEXT: [[TMP_16_A_FCA_1_GEP_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[TMP]], i64 16336; CHECK-NEXT: store <2 x ptr> [[A_FCA_1_EXTRACT]], ptr [[TMP_16_A_FCA_1_GEP_SROA_IDX]], align 16337; CHECK-NEXT: [[TMP_0_CAST:%.*]] = load <vscale x 4 x i64>, ptr [[TMP]], align 16338; CHECK-NEXT: ret <vscale x 4 x i64> [[TMP_0_CAST]]339;340 %tmp = alloca { <2 x ptr>, <2 x ptr> }341 store { <2 x ptr>, <2 x ptr> } %a, ptr %tmp342 %cast = load <vscale x 4 x i64>, ptr %tmp343 ret <vscale x 4 x i64> %cast344}345 346declare void @llvm.memcpy.p0.p0.i64(ptr nocapture, ptr nocapture, i64, i1) nounwind347;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:348; CHECK-MODIFY-CFG: {{.*}}349; CHECK-PRESERVE-CFG: {{.*}}350