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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -S -passes=sroa < %s | FileCheck %s3 4; Check that SROA can work with target extension types correctly.5 6target datalayout = "e-p:64:64:64-p1:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n8:16:32:64"7 8define target("spirv.DeviceEvent") @basic_alloc(target("spirv.DeviceEvent") %arg) {9; CHECK-LABEL: @basic_alloc(10; CHECK-NEXT: ret target("spirv.DeviceEvent") [[ARG:%.*]]11;12 %val = alloca target("spirv.DeviceEvent")13 store target("spirv.DeviceEvent") %arg, ptr %val14 %ret = load target("spirv.DeviceEvent"), ptr %val15 ret target("spirv.DeviceEvent") %ret16}17 18define target("spirv.DeviceEvent") @via_memcpy(target("spirv.DeviceEvent") %arg) {19; CHECK-LABEL: @via_memcpy(20; CHECK-NEXT: ret target("spirv.DeviceEvent") [[ARG:%.*]]21;22 %val = alloca target("spirv.DeviceEvent")23 %bar = alloca target("spirv.DeviceEvent")24 store target("spirv.DeviceEvent") %arg, ptr %val25 call void @llvm.memcpy.p0.p0.i64(ptr %bar, ptr %val, i64 8, i1 false)26 %ret = load target("spirv.DeviceEvent"), ptr %bar27 ret target("spirv.DeviceEvent") %ret28}29 30define target("spirv.DeviceEvent") @nobitcast(ptr %arg) {31; CHECK-LABEL: @nobitcast(32; CHECK-NEXT: [[VAL:%.*]] = alloca target("spirv.DeviceEvent"), align 833; CHECK-NEXT: store ptr [[ARG:%.*]], ptr [[VAL]], align 834; CHECK-NEXT: [[VAL_0_RET:%.*]] = load target("spirv.DeviceEvent"), ptr [[VAL]], align 835; CHECK-NEXT: ret target("spirv.DeviceEvent") [[VAL_0_RET]]36;37 %val = alloca target("spirv.DeviceEvent")38 store ptr %arg, ptr %val39 %ret = load target("spirv.DeviceEvent"), ptr %val40 ret target("spirv.DeviceEvent") %ret41}42 43define target("spirv.DeviceEvent") @viai64(target("spirv.DeviceEvent") %arg) {44; CHECK-LABEL: @viai64(45; CHECK-NEXT: [[VAL:%.*]] = alloca target("spirv.DeviceEvent"), align 846; CHECK-NEXT: [[BAR:%.*]] = alloca target("spirv.DeviceEvent"), align 847; CHECK-NEXT: store target("spirv.DeviceEvent") [[ARG:%.*]], ptr [[VAL]], align 848; CHECK-NEXT: [[VAL_0_IMEMCPY:%.*]] = load i64, ptr [[VAL]], align 849; CHECK-NEXT: store i64 [[VAL_0_IMEMCPY]], ptr [[BAR]], align 850; CHECK-NEXT: [[BAR_0_RET:%.*]] = load target("spirv.DeviceEvent"), ptr [[BAR]], align 851; CHECK-NEXT: ret target("spirv.DeviceEvent") [[BAR_0_RET]]52;53 %val = alloca target("spirv.DeviceEvent")54 %bar = alloca target("spirv.DeviceEvent")55 store target("spirv.DeviceEvent") %arg, ptr %val56 %imemcpy = load i64, ptr %val57 store i64 %imemcpy, ptr %bar58 %ret = load target("spirv.DeviceEvent"), ptr %bar59 ret target("spirv.DeviceEvent") %ret60}61 62declare void @llvm.memcpy.p0.p0.i64(ptr, ptr, i64, i1)63