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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt < %s -passes='sroa<preserve-cfg>' -S | FileCheck %s --check-prefixes=CHECK,CHECK-PRESERVE-CFG3; RUN: opt < %s -passes='sroa<modify-cfg>' -S | FileCheck %s --check-prefixes=CHECK,CHECK-MODIFY-CFG4target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n8:16:32:64"5 6define <4 x i1> @vector_bitcast() {7; CHECK-LABEL: @vector_bitcast(8; CHECK-NEXT: [[A:%.*]] = alloca <3 x i1>, align 19; CHECK-NEXT: store <3 x i1> <i1 true, i1 false, i1 true>, ptr [[A]], align 110; CHECK-NEXT: [[A_0_VEC:%.*]] = load <4 x i1>, ptr [[A]], align 111; CHECK-NEXT: ret <4 x i1> [[A_0_VEC]]12;13 %a = alloca <3 x i1>14 store <3 x i1> <i1 1,i1 0,i1 1>, ptr %a15 %vec = load <4 x i1>, ptr %a16 ret <4 x i1> %vec17}18 19define <64 x i16> @vector_bitcast_2(<32 x i16> %v) {20; CHECK-LABEL: @vector_bitcast_2(21; CHECK-NEXT: [[P:%.*]] = alloca <32 x i16>, align 6422; CHECK-NEXT: store <32 x i16> [[V:%.*]], ptr [[P]], align 6423; CHECK-NEXT: [[P_0_LOAD:%.*]] = load <64 x i16>, ptr [[P]], align 6424; CHECK-NEXT: ret <64 x i16> [[P_0_LOAD]]25;26 %p = alloca <32 x i16>27 store <32 x i16> %v, ptr %p28 %load = load <64 x i16>, ptr %p29 ret <64 x i16> %load30}31;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:32; CHECK-MODIFY-CFG: {{.*}}33; CHECK-PRESERVE-CFG: {{.*}}34