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1; REQUIRES: x86-registered-target2; RUN: opt < %s -passes='pseudo-probe,jump-threading' -S -o %t3; RUN: FileCheck %s < %t --check-prefix=JT4; RUN: llc -mtriple=x86_64-unknown-linux-gnu -function-sections <%t -filetype=asm | FileCheck %s --check-prefix=ASM5; RUN: llc -mtriple=x86_64-unknown-windows-msvc -function-sections <%t -filetype=asm | FileCheck %s --check-prefix=ASM6; RUN: opt < %s -passes='pseudo-probe' -S -o %t17; RUN: llc -mtriple=x86_64-- -stop-after=tailduplication <%t1 | FileCheck %s --check-prefix=MIR-tail8; RUN: opt < %s -passes='pseudo-probe,simplifycfg' -S | FileCheck %s --check-prefix=SC9 10declare i32 @f1()11 12define i32 @foo(i1 %cond) {13; JT-LABEL: @foo(14; JT: call void @llvm.pseudoprobe(i64 [[#GUID:]], i64 1, i32 0, i64 -1)15; ASM: pseudoprobe 6699318081062747564 1 0 016 %call = call i32 @f1()17 br i1 %cond, label %T, label %F18T:19 br label %Merge20F:21 br label %Merge22Merge:23;; Check branch T and F are gone, and their probes (probe 2 and 3) are gone too.24; JT-LABEL-NO: T25; JT-LABEL-NO: F26; JT-LABEL: Merge27; JT-NOT: call void @llvm.pseudoprobe(i64 [[#GUID:]], i64 428; JT-NOT: call void @llvm.pseudoprobe(i64 [[#GUID:]], i64 329; JT: call void @llvm.pseudoprobe(i64 [[#GUID:]], i64 5, i32 0, i64 -1)30; ASM-NOT: .pseudoprobe 6699318081062747564 431; ASM-NOT: .pseudoprobe 6699318081062747564 332; ASM: .pseudoprobe 6699318081062747564 5 0 033 ret i32 %call34}35 36;; Check block T and F are gone, and their probes (probe 2 and 3) are gone too.37; MIR-tail: bb.038; MIR-tail: PSEUDO_PROBE [[#GUID:]], 1, 0, 039; MIR-tail-NOT: PSEUDO_PROBE [[#GUID:]], 340; MIR-tail-NOT: PSEUDO_PROBE [[#GUID:]], 441; MIR-tail: PSEUDO_PROBE [[#GUID:]], 5, 0, 042 43 44define i32 @test(i32 %a, i32 %b, i32 %c) {45;; Check block bb1 and bb2 are gone, and their probes (probe 2 and 3) are gone too.46; SC-LABEL: @test(47; SC-LABEL-NO: bb148; SC-LABEL-NO: bb249; SC: [[T1:%.*]] = icmp eq i32 [[B:%.*]], 050; SC-NOT: call void @llvm.pseudoprobe(i64 [[#]], i64 251; SC-NOT: call void @llvm.pseudoprobe(i64 [[#]], i64 352; SC: [[T2:%.*]] = icmp sgt i32 [[C:%.*]], 153; SC: [[T3:%.*]] = add i32 [[A:%.*]], 154; SC: [[SPEC_SELECT:%.*]] = select i1 [[T2]], i32 [[T3]], i32 [[A]]55; SC: [[T4:%.*]] = select i1 [[T1]], i32 [[SPEC_SELECT]], i32 [[B]]56; SC: [[T5:%.*]] = sub i32 [[T4]], 157; SC: ret i32 [[T5]]58 59entry:60 %t1 = icmp eq i32 %b, 061 br i1 %t1, label %bb1, label %bb362 63bb1:64 %t2 = icmp sgt i32 %c, 165 br i1 %t2, label %bb2, label %bb366 67bb2:68 %t3 = add i32 %a, 169 br label %bb370 71bb3:72 %t4 = phi i32 [ %b, %entry ], [ %a, %bb1 ], [ %t3, %bb2 ]73 %t5 = sub i32 %t4, 174 ret i32 %t575}76