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1; REQUIRES: x86-registered-target2; RUN: opt < %s -codegenprepare -mtriple=x86_64 -S -o %t3; RUN: FileCheck %s < %t --check-prefix=IR4; RUN: llc -mtriple=x86_64-- -stop-after=finalize-isel %t -o - | FileCheck %s --check-prefix=MIR5 6define internal i32 @arc_compare(i1 %c) {7entry:8 %0 = load i64, ptr undef, align 89 br i1 %c, label %return, label %if.end10 11if.end: ; preds = %entry12;; Check pseudo probes are next to each other at the beginning of this block.13; IR-label: if.end14; IR: call void @llvm.pseudoprobe(i64 5116412291814990879, i64 1, i32 0, i64 -1)15; IR: call void @llvm.pseudoprobe(i64 5116412291814990879, i64 3, i32 0, i64 -1)16 call void @llvm.pseudoprobe(i64 5116412291814990879, i64 1, i32 0, i64 -1)17 %1 = load i16, ptr undef, align 818 call void @llvm.pseudoprobe(i64 5116412291814990879, i64 3, i32 0, i64 -1)19 %2 = and i16 %1, 1620 %3 = icmp eq i16 %2, 021;; Check the load-and-cmp sequence is fold into a test instruction.22; MIR-label: bb.1.if.end23; MIR: %[[#REG:]]:gr64 = IMPLICIT_DEF24; MIR: TEST8mi killed %[[#REG]], 1, $noreg, 0, $noreg, 1625; MIR: JCC_126 br i1 %3, label %return, label %if.end627 28if.end6: ; preds = %if.end29 call void @llvm.pseudoprobe(i64 5116412291814990879, i64 5, i32 0, i64 -1)30 br label %return31 32return: ; preds = %if.end6, %if.end, %entry33 ret i32 undef34}35 36; Function Attrs: inaccessiblememonly nounwind willreturn37declare void @llvm.pseudoprobe(i64, i64, i32, i64) #038 39attributes #0 = { inaccessiblememonly nounwind willreturn }40