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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -S %s -passes=scalarize-masked-mem-intrin -mtriple=amdgcn-amd-amdhsa | FileCheck %s3 4; COM: Test that, unlike on CPU targets, the mask doesn't get bitcast to a scalar,5; COM: since, on GPUs, each i1 takes up at least one register and so they should6; COM: be treated separately.7 8define <2 x i32> @scalarize_v2i32(<2 x ptr> %p, <2 x i1> %mask, <2 x i32> %passthru) {9; CHECK-LABEL: define <2 x i32> @scalarize_v2i32(10; CHECK-SAME: <2 x ptr> [[P:%.*]], <2 x i1> [[MASK:%.*]], <2 x i32> [[PASSTHRU:%.*]]) {11; CHECK-NEXT: [[MASK0:%.*]] = extractelement <2 x i1> [[MASK]], i64 012; CHECK-NEXT: br i1 [[MASK0]], label %[[COND_LOAD:.*]], label %[[ELSE:.*]]13; CHECK: [[COND_LOAD]]:14; CHECK-NEXT: [[PTR0:%.*]] = extractelement <2 x ptr> [[P]], i64 015; CHECK-NEXT: [[LOAD0:%.*]] = load i32, ptr [[PTR0]], align 816; CHECK-NEXT: [[RES0:%.*]] = insertelement <2 x i32> [[PASSTHRU]], i32 [[LOAD0]], i64 017; CHECK-NEXT: br label %[[ELSE]]18; CHECK: [[ELSE]]:19; CHECK-NEXT: [[RES_PHI_ELSE:%.*]] = phi <2 x i32> [ [[RES0]], %[[COND_LOAD]] ], [ [[PASSTHRU]], [[TMP0:%.*]] ]20; CHECK-NEXT: [[MASK1:%.*]] = extractelement <2 x i1> [[MASK]], i64 121; CHECK-NEXT: br i1 [[MASK1]], label %[[COND_LOAD1:.*]], label %[[ELSE2:.*]]22; CHECK: [[COND_LOAD1]]:23; CHECK-NEXT: [[PTR1:%.*]] = extractelement <2 x ptr> [[P]], i64 124; CHECK-NEXT: [[LOAD1:%.*]] = load i32, ptr [[PTR1]], align 825; CHECK-NEXT: [[RES1:%.*]] = insertelement <2 x i32> [[RES_PHI_ELSE]], i32 [[LOAD1]], i64 126; CHECK-NEXT: br label %[[ELSE2]]27; CHECK: [[ELSE2]]:28; CHECK-NEXT: [[RES_PHI_ELSE3:%.*]] = phi <2 x i32> [ [[RES1]], %[[COND_LOAD1]] ], [ [[RES_PHI_ELSE]], %[[ELSE]] ]29; CHECK-NEXT: ret <2 x i32> [[RES_PHI_ELSE3]]30;31 %ret = call <2 x i32> @llvm.masked.gather.v2i32.v2p0(<2 x ptr> %p, i32 8, <2 x i1> %mask, <2 x i32> %passthru)32 ret <2 x i32> %ret33}34 35declare <2 x i32> @llvm.masked.gather.v2i32.v2p0(<2 x ptr>, i32, <2 x i1>, <2 x i32>)36