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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -S %s -passes=scalarize-masked-mem-intrin -mtriple=amdgcn-amd-amdhsa | FileCheck %s3 4; COM: Test that, unlike on CPU targets, the mask doesn't get bitcast to a scalar,5; COM: since, on GPUs, each i1 takes up at least one register and so they should6; COM: be treated separately.7 8define void @scalarize_v2i32(<2 x ptr> %p, <2 x i1> %mask, <2 x i32> %value) {9; CHECK-LABEL: define void @scalarize_v2i32(10; CHECK-SAME: <2 x ptr> [[P:%.*]], <2 x i1> [[MASK:%.*]], <2 x i32> [[VALUE:%.*]]) {11; CHECK-NEXT: [[MASK0:%.*]] = extractelement <2 x i1> [[MASK]], i64 012; CHECK-NEXT: br i1 [[MASK0]], label %[[COND_STORE:.*]], label %[[ELSE:.*]]13; CHECK: [[COND_STORE]]:14; CHECK-NEXT: [[ELT0:%.*]] = extractelement <2 x i32> [[VALUE]], i64 015; CHECK-NEXT: [[PTR0:%.*]] = extractelement <2 x ptr> [[P]], i64 016; CHECK-NEXT: store i32 [[ELT0]], ptr [[PTR0]], align 817; CHECK-NEXT: br label %[[ELSE]]18; CHECK: [[ELSE]]:19; CHECK-NEXT: [[MASK1:%.*]] = extractelement <2 x i1> [[MASK]], i64 120; CHECK-NEXT: br i1 [[MASK1]], label %[[COND_STORE1:.*]], label %[[ELSE2:.*]]21; CHECK: [[COND_STORE1]]:22; CHECK-NEXT: [[ELT1:%.*]] = extractelement <2 x i32> [[VALUE]], i64 123; CHECK-NEXT: [[PTR1:%.*]] = extractelement <2 x ptr> [[P]], i64 124; CHECK-NEXT: store i32 [[ELT1]], ptr [[PTR1]], align 825; CHECK-NEXT: br label %[[ELSE2]]26; CHECK: [[ELSE2]]:27; CHECK-NEXT: ret void28;29 call void @llvm.masked.scatter.v2i32.v2p0(<2 x i32> %value, <2 x ptr> %p, i32 8, <2 x i1> %mask)30 ret void31}32 33declare void @llvm.masked.scatter.v2i32.v2p0(<2 x i32>, <2 x ptr>, i32, <2 x i1>)34