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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 42; RUN: opt -mtriple=amdgcn-- -S -passes=separate-const-offset-from-gep,gvn -reassociate-geps-verify-no-dead-code < %s | FileCheck -check-prefix=IR %s3 4target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"5 6@array = internal addrspace(4) constant [4096 x [32 x float]] zeroinitializer, align 47 8define amdgpu_kernel void @sum_of_array(i32 %x, i32 %y, ptr addrspace(1) nocapture %output) {9; IR-LABEL: define amdgpu_kernel void @sum_of_array(10; IR-SAME: i32 [[X:%.*]], i32 [[Y:%.*]], ptr addrspace(1) captures(none) [[OUTPUT:%.*]]) {11; IR-NEXT: [[TMP:%.*]] = sext i32 [[Y]] to i6412; IR-NEXT: [[TMP1:%.*]] = sext i32 [[X]] to i6413; IR-NEXT: [[TMP2:%.*]] = getelementptr [4096 x [32 x float]], ptr addrspace(4) @array, i64 0, i64 [[TMP1]], i64 [[TMP]]14; IR-NEXT: [[TMP82:%.*]] = getelementptr i8, ptr addrspace(4) [[TMP2]], i64 415; IR-NEXT: [[TMP144:%.*]] = getelementptr i8, ptr addrspace(4) [[TMP2]], i64 12816; IR-NEXT: [[TMP187:%.*]] = getelementptr i8, ptr addrspace(4) [[TMP2]], i64 13217; IR-NEXT: store float 0.000000e+00, ptr addrspace(1) [[OUTPUT]], align 418; IR-NEXT: ret void19;20 %tmp = sext i32 %y to i6421 %tmp1 = sext i32 %x to i6422 %tmp2 = getelementptr inbounds [4096 x [32 x float]], ptr addrspace(4) @array, i64 0, i64 %tmp1, i64 %tmp23 %tmp4 = load float, ptr addrspace(4) %tmp2, align 424 %tmp5 = fadd float %tmp4, 0.000000e+0025 %tmp6 = add i32 %y, 126 %tmp7 = sext i32 %tmp6 to i6427 %tmp8 = getelementptr inbounds [4096 x [32 x float]], ptr addrspace(4) @array, i64 0, i64 %tmp1, i64 %tmp728 %tmp10 = load float, ptr addrspace(4) %tmp8, align 429 %tmp11 = fadd float %tmp5, %tmp1030 %tmp12 = add i32 %x, 131 %tmp13 = sext i32 %tmp12 to i6432 %tmp14 = getelementptr inbounds [4096 x [32 x float]], ptr addrspace(4) @array, i64 0, i64 %tmp13, i64 %tmp33 %tmp16 = load float, ptr addrspace(4) %tmp14, align 434 %tmp17 = fadd float %tmp11, %tmp1635 %tmp18 = getelementptr inbounds [4096 x [32 x float]], ptr addrspace(4) @array, i64 0, i64 %tmp13, i64 %tmp736 %tmp20 = load float, ptr addrspace(4) %tmp18, align 437 %tmp21 = fadd float %tmp17, %tmp2038 store float %tmp21, ptr addrspace(1) %output, align 439 ret void40}41 42@array2 = internal addrspace(4) constant [4096 x [4 x float]] zeroinitializer, align 443 44; Some of the indices go over the maximum mubuf offset, so don't split them.45 46define amdgpu_kernel void @sum_of_array_over_max_mubuf_offset(i32 %x, i32 %y, ptr addrspace(1) nocapture %output) {47; IR-LABEL: define amdgpu_kernel void @sum_of_array_over_max_mubuf_offset(48; IR-SAME: i32 [[X:%.*]], i32 [[Y:%.*]], ptr addrspace(1) captures(none) [[OUTPUT:%.*]]) {49; IR-NEXT: [[TMP:%.*]] = sext i32 [[Y]] to i6450; IR-NEXT: [[TMP1:%.*]] = sext i32 [[X]] to i6451; IR-NEXT: [[TMP2:%.*]] = getelementptr [4096 x [4 x float]], ptr addrspace(4) @array2, i64 0, i64 [[TMP1]], i64 [[TMP]]52; IR-NEXT: [[TMP6:%.*]] = add i32 [[Y]], 25553; IR-NEXT: [[TMP7:%.*]] = sext i32 [[TMP6]] to i6454; IR-NEXT: [[TMP82:%.*]] = getelementptr i8, ptr addrspace(4) [[TMP2]], i64 102055; IR-NEXT: [[TMP12:%.*]] = add i32 [[X]], 25656; IR-NEXT: [[TMP13:%.*]] = sext i32 [[TMP12]] to i6457; IR-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4096 x [4 x float]], ptr addrspace(4) @array2, i64 0, i64 [[TMP13]], i64 [[TMP]]58; IR-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4096 x [4 x float]], ptr addrspace(4) @array2, i64 0, i64 [[TMP13]], i64 [[TMP7]]59; IR-NEXT: store float 0.000000e+00, ptr addrspace(1) [[OUTPUT]], align 460; IR-NEXT: ret void61;62 %tmp = sext i32 %y to i6463 %tmp1 = sext i32 %x to i6464 %tmp2 = getelementptr inbounds [4096 x [4 x float]], ptr addrspace(4) @array2, i64 0, i64 %tmp1, i64 %tmp65 %tmp4 = load float, ptr addrspace(4) %tmp2, align 466 %tmp5 = fadd float %tmp4, 0.000000e+0067 %tmp6 = add i32 %y, 25568 %tmp7 = sext i32 %tmp6 to i6469 %tmp8 = getelementptr inbounds [4096 x [4 x float]], ptr addrspace(4) @array2, i64 0, i64 %tmp1, i64 %tmp770 %tmp10 = load float, ptr addrspace(4) %tmp8, align 471 %tmp11 = fadd float %tmp5, %tmp1072 %tmp12 = add i32 %x, 25673 %tmp13 = sext i32 %tmp12 to i6474 %tmp14 = getelementptr inbounds [4096 x [4 x float]], ptr addrspace(4) @array2, i64 0, i64 %tmp13, i64 %tmp75 %tmp16 = load float, ptr addrspace(4) %tmp14, align 476 %tmp17 = fadd float %tmp11, %tmp1677 %tmp18 = getelementptr inbounds [4096 x [4 x float]], ptr addrspace(4) @array2, i64 0, i64 %tmp13, i64 %tmp778 %tmp20 = load float, ptr addrspace(4) %tmp18, align 479 %tmp21 = fadd float %tmp17, %tmp2080 store float %tmp21, ptr addrspace(1) %output, align 481 ret void82}83 84 85@lds_array = internal addrspace(3) global [4096 x [4 x float]] undef, align 486 87; DS instructions have a larger immediate offset, so make sure these are OK.88define amdgpu_kernel void @sum_of_lds_array_over_max_mubuf_offset(i32 %x, i32 %y, ptr addrspace(1) nocapture %output) {89; IR-LABEL: define amdgpu_kernel void @sum_of_lds_array_over_max_mubuf_offset(90; IR-SAME: i32 [[X:%.*]], i32 [[Y:%.*]], ptr addrspace(1) captures(none) [[OUTPUT:%.*]]) {91; IR-NEXT: [[TMP2:%.*]] = getelementptr [4096 x [4 x float]], ptr addrspace(3) @lds_array, i32 0, i32 [[X]], i32 [[Y]]92; IR-NEXT: [[TMP4:%.*]] = load float, ptr addrspace(3) [[TMP2]], align 493; IR-NEXT: [[TMP5:%.*]] = fadd float [[TMP4]], 0.000000e+0094; IR-NEXT: [[TMP82:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP2]], i32 102095; IR-NEXT: [[TMP10:%.*]] = load float, ptr addrspace(3) [[TMP82]], align 496; IR-NEXT: [[TMP11:%.*]] = fadd float [[TMP5]], [[TMP10]]97; IR-NEXT: [[TMP144:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP2]], i32 6451298; IR-NEXT: [[TMP16:%.*]] = load float, ptr addrspace(3) [[TMP144]], align 499; IR-NEXT: [[TMP17:%.*]] = fadd float [[TMP11]], [[TMP16]]100; IR-NEXT: [[TMP187:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP2]], i32 65532101; IR-NEXT: [[TMP20:%.*]] = load float, ptr addrspace(3) [[TMP187]], align 4102; IR-NEXT: [[TMP21:%.*]] = fadd float [[TMP17]], [[TMP20]]103; IR-NEXT: store float [[TMP21]], ptr addrspace(1) [[OUTPUT]], align 4104; IR-NEXT: ret void105;106 %tmp2 = getelementptr inbounds [4096 x [4 x float]], ptr addrspace(3) @lds_array, i32 0, i32 %x, i32 %y107 %tmp4 = load float, ptr addrspace(3) %tmp2, align 4108 %tmp5 = fadd float %tmp4, 0.000000e+00109 %tmp6 = add i32 %y, 255110 %tmp8 = getelementptr inbounds [4096 x [4 x float]], ptr addrspace(3) @lds_array, i32 0, i32 %x, i32 %tmp6111 %tmp10 = load float, ptr addrspace(3) %tmp8, align 4112 %tmp11 = fadd float %tmp5, %tmp10113 %tmp12 = add i32 %x, 4032114 %tmp14 = getelementptr inbounds [4096 x [4 x float]], ptr addrspace(3) @lds_array, i32 0, i32 %tmp12, i32 %y115 %tmp16 = load float, ptr addrspace(3) %tmp14, align 4116 %tmp17 = fadd float %tmp11, %tmp16117 %tmp18 = getelementptr inbounds [4096 x [4 x float]], ptr addrspace(3) @lds_array, i32 0, i32 %tmp12, i32 %tmp6118 %tmp20 = load float, ptr addrspace(3) %tmp18, align 4119 %tmp21 = fadd float %tmp17, %tmp20120 store float %tmp21, ptr addrspace(1) %output, align 4121 ret void122}123 124define amdgpu_ps <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> @keep_metadata(ptr addrspace(4) inreg noalias dereferenceable(18446744073709551615), ptr addrspace(4) inreg noalias dereferenceable(18446744073709551615), ptr addrspace(4) inreg noalias dereferenceable(18446744073709551615), ptr addrspace(4) inreg noalias dereferenceable(18446744073709551615), float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, i32, i32, float, i32) #5 {125; IR-LABEL: define amdgpu_ps <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> @keep_metadata(126; IR-SAME: ptr addrspace(4) inreg noalias dereferenceable(18446744073709551615) [[TMP0:%.*]], ptr addrspace(4) inreg noalias dereferenceable(18446744073709551615) [[TMP1:%.*]], ptr addrspace(4) inreg noalias dereferenceable(18446744073709551615) [[TMP2:%.*]], ptr addrspace(4) inreg noalias dereferenceable(18446744073709551615) [[TMP3:%.*]], float inreg [[TMP4:%.*]], i32 inreg [[TMP5:%.*]], <2 x i32> [[TMP6:%.*]], <2 x i32> [[TMP7:%.*]], <2 x i32> [[TMP8:%.*]], <3 x i32> [[TMP9:%.*]], <2 x i32> [[TMP10:%.*]], <2 x i32> [[TMP11:%.*]], <2 x i32> [[TMP12:%.*]], float [[TMP13:%.*]], float [[TMP14:%.*]], float [[TMP15:%.*]], float [[TMP16:%.*]], float [[TMP17:%.*]], i32 [[TMP18:%.*]], i32 [[TMP19:%.*]], float [[TMP20:%.*]], i32 [[TMP21:%.*]]) #[[ATTR0:[0-9]+]] {127; IR-NEXT: main_body:128; IR-NEXT: [[TMP22:%.*]] = call nsz float @llvm.amdgcn.interp.mov(i32 2, i32 0, i32 0, i32 [[TMP5]]) #[[ATTR3:[0-9]+]]129; IR-NEXT: [[TMP23:%.*]] = bitcast float [[TMP22]] to i32130; IR-NEXT: [[TMP24:%.*]] = shl i32 [[TMP23]], 1131; IR-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP24]] to i64132; IR-NEXT: [[TMP25:%.*]] = getelementptr [0 x <8 x i32>], ptr addrspace(4) [[TMP1]], i64 0, i64 [[IDXPROM1]], !amdgpu.uniform [[META0:![0-9]+]]133; IR-NEXT: [[TMP26:%.*]] = load <8 x i32>, ptr addrspace(4) [[TMP25]], align 32, !invariant.load [[META0]]134; IR-NEXT: [[TMP27:%.*]] = shl i32 [[TMP23]], 2135; IR-NEXT: [[TMP28:%.*]] = sext i32 [[TMP27]] to i64136; IR-NEXT: [[TMP29:%.*]] = getelementptr [0 x <4 x i32>], ptr addrspace(4) [[TMP1]], i64 0, i64 [[TMP28]], !amdgpu.uniform [[META0]]137; IR-NEXT: [[TMP30:%.*]] = getelementptr i8, ptr addrspace(4) [[TMP29]], i64 48, !amdgpu.uniform [[META0]]138; IR-NEXT: [[TMP31:%.*]] = load <4 x i32>, ptr addrspace(4) [[TMP30]], align 16, !invariant.load [[META0]]139; IR-NEXT: [[TMP32:%.*]] = call nsz <4 x float> @llvm.amdgcn.image.sample.v4f32.v2f32.v8i32(<2 x float> zeroinitializer, <8 x i32> [[TMP26]], <4 x i32> [[TMP31]], i32 15, i1 false, i1 false, i1 false, i1 false, i1 false) #[[ATTR3]]140; IR-NEXT: [[TMP33:%.*]] = extractelement <4 x float> [[TMP32]], i32 0141; IR-NEXT: [[TMP34:%.*]] = extractelement <4 x float> [[TMP32]], i32 1142; IR-NEXT: [[TMP35:%.*]] = extractelement <4 x float> [[TMP32]], i32 2143; IR-NEXT: [[TMP36:%.*]] = extractelement <4 x float> [[TMP32]], i32 3144; IR-NEXT: [[TMP37:%.*]] = bitcast float [[TMP4]] to i32145; IR-NEXT: [[TMP38:%.*]] = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> undef, i32 [[TMP37]], 4146; IR-NEXT: [[TMP39:%.*]] = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> [[TMP38]], float [[TMP33]], 5147; IR-NEXT: [[TMP40:%.*]] = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> [[TMP39]], float [[TMP34]], 6148; IR-NEXT: [[TMP41:%.*]] = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> [[TMP40]], float [[TMP35]], 7149; IR-NEXT: [[TMP42:%.*]] = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> [[TMP41]], float [[TMP36]], 8150; IR-NEXT: [[TMP43:%.*]] = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> [[TMP42]], float [[TMP20]], 19151; IR-NEXT: ret <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> [[TMP43]]152;153main_body:154 %22 = call nsz float @llvm.amdgcn.interp.mov(i32 2, i32 0, i32 0, i32 %5) #8155 %23 = bitcast float %22 to i32156 %24 = shl i32 %23, 1157 %25 = getelementptr [0 x <8 x i32>], ptr addrspace(4) %1, i32 0, i32 %24, !amdgpu.uniform !0158 %26 = load <8 x i32>, ptr addrspace(4) %25, align 32, !invariant.load !0159 %27 = shl i32 %23, 2160 %28 = or disjoint i32 %27, 3161 %29 = getelementptr [0 x <4 x i32>], ptr addrspace(4) %1, i32 0, i32 %28, !amdgpu.uniform !0162 %30 = load <4 x i32>, ptr addrspace(4) %29, align 16, !invariant.load !0163 %31 = call nsz <4 x float> @llvm.amdgcn.image.sample.v4f32.v2f32.v8i32(<2 x float> zeroinitializer, <8 x i32> %26, <4 x i32> %30, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false) #8164 %32 = extractelement <4 x float> %31, i32 0165 %33 = extractelement <4 x float> %31, i32 1166 %34 = extractelement <4 x float> %31, i32 2167 %35 = extractelement <4 x float> %31, i32 3168 %36 = bitcast float %4 to i32169 %37 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> undef, i32 %36, 4170 %38 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %37, float %32, 5171 %39 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %38, float %33, 6172 %40 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %39, float %34, 7173 %41 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %40, float %35, 8174 %42 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %41, float %20, 19175 ret <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %42176}177 178; Function Attrs: nounwind readnone speculatable179declare float @llvm.amdgcn.interp.mov(i32, i32, i32, i32) #6180 181; Function Attrs: nounwind readonly182declare <4 x float> @llvm.amdgcn.image.sample.v4f32.v2f32.v8i32(<2 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #7183 184 185!0 = !{}186 187attributes #5 = { "InitialPSInputAddr"="45175" }188attributes #6 = { nounwind readnone speculatable }189attributes #7 = { nounwind readonly }190attributes #8 = { nounwind readnone }191;.192; IR: [[META0]] = !{}193;.194