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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; Test the xor with constant operand is decomposed in to gep.3; RUN: opt -mtriple=amdgcn-amd-amdhsa -passes=separate-const-offset-from-gep \4; RUN: -S < %s | FileCheck %s5; Test the gvn pass eliminates the redundant xor instructions from decomposition.6; RUN: opt -mtriple=amdgcn-amd-amdhsa -passes=separate-const-offset-from-gep,gvn \7; RUN: -S < %s | FileCheck --check-prefix=GVN %s8 9; Check that disjoint constants are properly extracted and folded into GEP10; addressing modes and GVN to eliminate redundant computations11define amdgpu_kernel void @test1(i1 %0, ptr addrspace(3) %1) {12; CHECK-LABEL: define amdgpu_kernel void @test1(13; CHECK-SAME: i1 [[TMP0:%.*]], ptr addrspace(3) [[TMP1:%.*]]) {14; CHECK-NEXT: [[ENTRY:.*:]]15; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP0]], i32 0, i32 28816; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 3217; CHECK-NEXT: [[TMP4:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP3]]18; CHECK-NEXT: [[TMP5:%.*]] = xor i32 [[TMP2]], 3219; CHECK-NEXT: [[TMP6:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP5]]20; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP6]], i32 819221; CHECK-NEXT: [[TMP8:%.*]] = xor i32 [[TMP2]], 3222; CHECK-NEXT: [[TMP9:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP8]]23; CHECK-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP9]], i32 1638424; CHECK-NEXT: [[TMP11:%.*]] = xor i32 [[TMP2]], 3225; CHECK-NEXT: [[TMP12:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP11]]26; CHECK-NEXT: [[TMP13:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP12]], i32 2457627; CHECK-NEXT: [[TMP14:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP4]], align 1628; CHECK-NEXT: [[TMP15:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP7]], align 1629; CHECK-NEXT: [[TMP16:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP10]], align 1630; CHECK-NEXT: [[TMP17:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP13]], align 1631; CHECK-NEXT: [[TMP18:%.*]] = fadd <8 x half> [[TMP14]], [[TMP15]]32; CHECK-NEXT: [[TMP19:%.*]] = fadd <8 x half> [[TMP16]], [[TMP17]]33; CHECK-NEXT: [[TMP20:%.*]] = fadd <8 x half> [[TMP18]], [[TMP19]]34; CHECK-NEXT: store <8 x half> [[TMP20]], ptr addrspace(3) [[TMP1]], align 1635; CHECK-NEXT: ret void36;37; GVN-LABEL: define amdgpu_kernel void @test1(38; GVN-SAME: i1 [[TMP0:%.*]], ptr addrspace(3) [[TMP1:%.*]]) {39; GVN-NEXT: [[ENTRY:.*:]]40; GVN-NEXT: [[TMP2:%.*]] = select i1 [[TMP0]], i32 0, i32 28841; GVN-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 3242; GVN-NEXT: [[TMP4:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP3]]43; GVN-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP4]], i32 819244; GVN-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP4]], i32 1638445; GVN-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP4]], i32 2457646; GVN-NEXT: [[TMP8:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP4]], align 1647; GVN-NEXT: [[TMP9:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP5]], align 1648; GVN-NEXT: [[TMP10:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP6]], align 1649; GVN-NEXT: [[TMP11:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP7]], align 1650; GVN-NEXT: [[TMP12:%.*]] = fadd <8 x half> [[TMP8]], [[TMP9]]51; GVN-NEXT: [[TMP13:%.*]] = fadd <8 x half> [[TMP10]], [[TMP11]]52; GVN-NEXT: [[TMP14:%.*]] = fadd <8 x half> [[TMP12]], [[TMP13]]53; GVN-NEXT: store <8 x half> [[TMP14]], ptr addrspace(3) [[TMP1]], align 1654; GVN-NEXT: ret void55;56entry:57 %2 = select i1 %0, i32 0, i32 28858 %3 = xor i32 %2, 3259 %4 = xor i32 %2, 412860 %5 = xor i32 %2, 822461 %6 = xor i32 %2, 1232062 %7 = getelementptr half, ptr addrspace(3) %1, i32 %363 %8 = getelementptr half, ptr addrspace(3) %1, i32 %464 %9 = getelementptr half, ptr addrspace(3) %1, i32 %565 %10 = getelementptr half, ptr addrspace(3) %1, i32 %666 %11 = load <8 x half>, ptr addrspace(3) %7, align 1667 %12 = load <8 x half>, ptr addrspace(3) %8, align 1668 %13 = load <8 x half>, ptr addrspace(3) %9, align 1669 %14 = load <8 x half>, ptr addrspace(3) %10, align 1670 %15 = fadd <8 x half> %11, %1271 %16 = fadd <8 x half> %13, %1472 %17 = fadd <8 x half> %15, %1673 store <8 x half> %17, ptr addrspace(3) %1, align 1674 ret void75}76 77; Check that disjoint constants are properly extracted and folded into GEP78; addressing modes and GVN to eliminate redundant computations79define amdgpu_kernel void @test2(i1 %0, ptr addrspace(3) %1) {80; CHECK-LABEL: define amdgpu_kernel void @test2(81; CHECK-SAME: i1 [[TMP0:%.*]], ptr addrspace(3) [[TMP1:%.*]]) {82; CHECK-NEXT: [[ENTRY:.*:]]83; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP0]], i32 0, i32 28884; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 3285; CHECK-NEXT: [[TMP4:%.*]] = xor i32 [[TMP2]], 3286; CHECK-NEXT: [[TMP5:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP4]]87; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP5]], i32 2457688; CHECK-NEXT: [[TMP7:%.*]] = xor i32 [[TMP2]], 3289; CHECK-NEXT: [[TMP8:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP7]]90; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP8]], i32 1638491; CHECK-NEXT: [[TMP10:%.*]] = xor i32 [[TMP2]], 3292; CHECK-NEXT: [[TMP11:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP10]]93; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP11]], i32 819294; CHECK-NEXT: [[TMP13:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP3]]95; CHECK-NEXT: [[TMP14:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP6]], align 1696; CHECK-NEXT: [[TMP15:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP9]], align 1697; CHECK-NEXT: [[TMP16:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP12]], align 1698; CHECK-NEXT: [[TMP17:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP13]], align 1699; CHECK-NEXT: [[TMP18:%.*]] = fadd <8 x half> [[TMP14]], [[TMP15]]100; CHECK-NEXT: [[TMP19:%.*]] = fadd <8 x half> [[TMP16]], [[TMP17]]101; CHECK-NEXT: [[TMP20:%.*]] = fadd <8 x half> [[TMP18]], [[TMP19]]102; CHECK-NEXT: store <8 x half> [[TMP20]], ptr addrspace(3) [[TMP1]], align 16103; CHECK-NEXT: ret void104;105; GVN-LABEL: define amdgpu_kernel void @test2(106; GVN-SAME: i1 [[TMP0:%.*]], ptr addrspace(3) [[TMP1:%.*]]) {107; GVN-NEXT: [[ENTRY:.*:]]108; GVN-NEXT: [[TMP2:%.*]] = select i1 [[TMP0]], i32 0, i32 288109; GVN-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 32110; GVN-NEXT: [[TMP4:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP3]]111; GVN-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP4]], i32 24576112; GVN-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP4]], i32 16384113; GVN-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP4]], i32 8192114; GVN-NEXT: [[TMP8:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP5]], align 16115; GVN-NEXT: [[TMP9:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP6]], align 16116; GVN-NEXT: [[TMP10:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP7]], align 16117; GVN-NEXT: [[TMP11:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP4]], align 16118; GVN-NEXT: [[TMP12:%.*]] = fadd <8 x half> [[TMP8]], [[TMP9]]119; GVN-NEXT: [[TMP13:%.*]] = fadd <8 x half> [[TMP10]], [[TMP11]]120; GVN-NEXT: [[TMP14:%.*]] = fadd <8 x half> [[TMP12]], [[TMP13]]121; GVN-NEXT: store <8 x half> [[TMP14]], ptr addrspace(3) [[TMP1]], align 16122; GVN-NEXT: ret void123;124entry:125 %2 = select i1 %0, i32 0, i32 288126 %3 = xor i32 %2, 12320127 %4 = xor i32 %2, 8224128 %5 = xor i32 %2, 4128129 %6 = xor i32 %2, 32130 %7 = getelementptr half, ptr addrspace(3) %1, i32 %3131 %8 = getelementptr half, ptr addrspace(3) %1, i32 %4132 %9 = getelementptr half, ptr addrspace(3) %1, i32 %5133 %10 = getelementptr half, ptr addrspace(3) %1, i32 %6134 %11 = load <8 x half>, ptr addrspace(3) %7, align 16135 %12 = load <8 x half>, ptr addrspace(3) %8, align 16136 %13 = load <8 x half>, ptr addrspace(3) %9, align 16137 %14 = load <8 x half>, ptr addrspace(3) %10, align 16138 %15 = fadd <8 x half> %11, %12139 %16 = fadd <8 x half> %13, %14140 %17 = fadd <8 x half> %15, %16141 store <8 x half> %17, ptr addrspace(3) %1, align 16142 ret void143}144 145; Verify that xor instructions with different non-disjoint constants are optimized146define amdgpu_kernel void @test3(i1 %0, ptr addrspace(3) %1) {147; CHECK-LABEL: define amdgpu_kernel void @test3(148; CHECK-SAME: i1 [[TMP0:%.*]], ptr addrspace(3) [[TMP1:%.*]]) {149; CHECK-NEXT: [[ENTRY:.*:]]150; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP0]], i32 0, i32 288151; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 32152; CHECK-NEXT: [[TMP4:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP3]]153; CHECK-NEXT: [[TMP5:%.*]] = xor i32 [[TMP2]], 288154; CHECK-NEXT: [[TMP6:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP5]]155; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP6]], i32 4096156; CHECK-NEXT: [[TMP8:%.*]] = xor i32 [[TMP2]], 32157; CHECK-NEXT: [[TMP9:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP8]]158; CHECK-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP9]], i32 8192159; CHECK-NEXT: [[TMP11:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP4]], align 16160; CHECK-NEXT: [[TMP12:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP7]], align 16161; CHECK-NEXT: [[TMP13:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP10]], align 16162; CHECK-NEXT: [[TMP14:%.*]] = fadd <8 x half> [[TMP11]], [[TMP12]]163; CHECK-NEXT: [[TMP15:%.*]] = fadd <8 x half> [[TMP13]], [[TMP14]]164; CHECK-NEXT: store <8 x half> [[TMP15]], ptr addrspace(3) [[TMP1]], align 16165; CHECK-NEXT: ret void166;167; GVN-LABEL: define amdgpu_kernel void @test3(168; GVN-SAME: i1 [[TMP0:%.*]], ptr addrspace(3) [[TMP1:%.*]]) {169; GVN-NEXT: [[ENTRY:.*:]]170; GVN-NEXT: [[TMP2:%.*]] = select i1 [[TMP0]], i32 0, i32 288171; GVN-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 32172; GVN-NEXT: [[TMP4:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP3]]173; GVN-NEXT: [[TMP5:%.*]] = xor i32 [[TMP2]], 288174; GVN-NEXT: [[TMP6:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP5]]175; GVN-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP6]], i32 4096176; GVN-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP4]], i32 8192177; GVN-NEXT: [[TMP9:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP4]], align 16178; GVN-NEXT: [[TMP10:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP7]], align 16179; GVN-NEXT: [[TMP11:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP8]], align 16180; GVN-NEXT: [[TMP12:%.*]] = fadd <8 x half> [[TMP9]], [[TMP10]]181; GVN-NEXT: [[TMP13:%.*]] = fadd <8 x half> [[TMP11]], [[TMP12]]182; GVN-NEXT: store <8 x half> [[TMP13]], ptr addrspace(3) [[TMP1]], align 16183; GVN-NEXT: ret void184;185entry:186 %2 = select i1 %0, i32 0, i32 288187 %3 = xor i32 %2, 32188 %4 = xor i32 %2, 2336189 %5 = xor i32 %2, 4128190 %6 = getelementptr half, ptr addrspace(3) %1, i32 %3191 %7 = getelementptr half, ptr addrspace(3) %1, i32 %4192 %8 = getelementptr half, ptr addrspace(3) %1, i32 %5193 %9 = load <8 x half>, ptr addrspace(3) %6, align 16194 %10 = load <8 x half>, ptr addrspace(3) %7, align 16195 %11 = load <8 x half>, ptr addrspace(3) %8, align 16196 %12 = fadd <8 x half> %9, %10197 %13 = fadd <8 x half> %11, %12198 store <8 x half> %13, ptr addrspace(3) %1, align 16199 ret void200}201 202; Verify that no optimization occurs when disjoint constants are absent203define amdgpu_kernel void @test4(i1 %0, ptr addrspace(3) %1) {204; CHECK-LABEL: define amdgpu_kernel void @test4(205; CHECK-SAME: i1 [[TMP0:%.*]], ptr addrspace(3) [[TMP1:%.*]]) {206; CHECK-NEXT: [[ENTRY:.*:]]207; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP0]], i32 0, i32 288208; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 32209; CHECK-NEXT: [[TMP4:%.*]] = xor i32 [[TMP2]], 288210; CHECK-NEXT: [[TMP5:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP3]]211; CHECK-NEXT: [[TMP6:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP4]]212; CHECK-NEXT: [[TMP7:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP5]], align 16213; CHECK-NEXT: [[TMP8:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP6]], align 16214; CHECK-NEXT: [[TMP9:%.*]] = fadd <8 x half> [[TMP7]], [[TMP8]]215; CHECK-NEXT: store <8 x half> [[TMP9]], ptr addrspace(3) [[TMP1]], align 16216; CHECK-NEXT: ret void217;218; GVN-LABEL: define amdgpu_kernel void @test4(219; GVN-SAME: i1 [[TMP0:%.*]], ptr addrspace(3) [[TMP1:%.*]]) {220; GVN-NEXT: [[ENTRY:.*:]]221; GVN-NEXT: [[TMP2:%.*]] = select i1 [[TMP0]], i32 0, i32 288222; GVN-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 32223; GVN-NEXT: [[TMP4:%.*]] = xor i32 [[TMP2]], 288224; GVN-NEXT: [[TMP5:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP3]]225; GVN-NEXT: [[TMP6:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP4]]226; GVN-NEXT: [[TMP7:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP5]], align 16227; GVN-NEXT: [[TMP8:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP6]], align 16228; GVN-NEXT: [[TMP9:%.*]] = fadd <8 x half> [[TMP7]], [[TMP8]]229; GVN-NEXT: store <8 x half> [[TMP9]], ptr addrspace(3) [[TMP1]], align 16230; GVN-NEXT: ret void231;232entry:233 %2 = select i1 %0, i32 0, i32 288234 %3 = xor i32 %2, 32235 %4 = xor i32 %2, 288236 %5 = getelementptr half, ptr addrspace(3) %1, i32 %3237 %6 = getelementptr half, ptr addrspace(3) %1, i32 %4238 %7 = load <8 x half>, ptr addrspace(3) %5, align 16239 %8 = load <8 x half>, ptr addrspace(3) %6, align 16240 %9 = fadd <8 x half> %7, %8241 store <8 x half> %9, ptr addrspace(3) %1, align 16242 ret void243}244 245 246; Verify that XOR-BinOp-GEP usage chains are properly optimized247define amdgpu_kernel void @test5(i1 %0, ptr addrspace(3) %1) {248; CHECK-LABEL: define amdgpu_kernel void @test5(249; CHECK-SAME: i1 [[TMP0:%.*]], ptr addrspace(3) [[TMP1:%.*]]) {250; CHECK-NEXT: [[ENTRY:.*:]]251; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP0]], i32 0, i32 288252; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 32253; CHECK-NEXT: [[TMP4:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP3]]254; CHECK-NEXT: [[TMP5:%.*]] = xor i32 [[TMP2]], 32255; CHECK-NEXT: [[TMP6:%.*]] = add i32 [[TMP5]], 256256; CHECK-NEXT: [[TMP7:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP6]]257; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP7]], i32 8192258; CHECK-NEXT: [[TMP9:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP4]], align 16259; CHECK-NEXT: [[TMP10:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP8]], align 16260; CHECK-NEXT: [[TMP11:%.*]] = fadd <8 x half> [[TMP9]], [[TMP10]]261; CHECK-NEXT: store <8 x half> [[TMP11]], ptr addrspace(3) [[TMP1]], align 16262; CHECK-NEXT: ret void263;264; GVN-LABEL: define amdgpu_kernel void @test5(265; GVN-SAME: i1 [[TMP0:%.*]], ptr addrspace(3) [[TMP1:%.*]]) {266; GVN-NEXT: [[ENTRY:.*:]]267; GVN-NEXT: [[TMP2:%.*]] = select i1 [[TMP0]], i32 0, i32 288268; GVN-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 32269; GVN-NEXT: [[TMP4:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP3]]270; GVN-NEXT: [[TMP5:%.*]] = add i32 [[TMP3]], 256271; GVN-NEXT: [[TMP6:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP5]]272; GVN-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP6]], i32 8192273; GVN-NEXT: [[TMP8:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP4]], align 16274; GVN-NEXT: [[TMP9:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP7]], align 16275; GVN-NEXT: [[TMP10:%.*]] = fadd <8 x half> [[TMP8]], [[TMP9]]276; GVN-NEXT: store <8 x half> [[TMP10]], ptr addrspace(3) [[TMP1]], align 16277; GVN-NEXT: ret void278;279entry:280 %2 = select i1 %0, i32 0, i32 288281 %3 = xor i32 %2, 32282 %4 = xor i32 %2, 4128283 %5 = add i32 %4, 256284 %6 = getelementptr half, ptr addrspace(3) %1, i32 %3285 %7 = getelementptr half, ptr addrspace(3) %1, i32 %5286 %8 = load <8 x half>, ptr addrspace(3) %6, align 16287 %9 = load <8 x half>, ptr addrspace(3) %7, align 16288 %10 = fadd <8 x half> %8, %9289 store <8 x half> %10, ptr addrspace(3) %1, align 16290 ret void291}292 293; Verify that BinOp-XOR-GEP usage chains are properly optimized.294; In the below test, make sure we stop processing the chain at xor295; and not fold the constant from add instruction in to gep. The296; constant from add can be folded and the future work will cover297; these cases.298define amdgpu_kernel void @test6(i1 %0, ptr addrspace(3) %1) {299; CHECK-LABEL: define amdgpu_kernel void @test6(300; CHECK-SAME: i1 [[TMP0:%.*]], ptr addrspace(3) [[TMP1:%.*]]) {301; CHECK-NEXT: [[ENTRY:.*:]]302; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP0]], i32 0, i32 288303; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 32304; CHECK-NEXT: [[TMP4:%.*]] = add i32 [[TMP2]], 256305; CHECK-NEXT: [[TMP5:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP3]]306; CHECK-NEXT: [[TMP6:%.*]] = xor i32 [[TMP4]], 32307; CHECK-NEXT: [[TMP7:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP6]]308; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP7]], i32 8192309; CHECK-NEXT: [[TMP9:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP5]], align 16310; CHECK-NEXT: [[TMP10:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP8]], align 16311; CHECK-NEXT: [[TMP11:%.*]] = fadd <8 x half> [[TMP9]], [[TMP10]]312; CHECK-NEXT: store <8 x half> [[TMP11]], ptr addrspace(3) [[TMP1]], align 16313; CHECK-NEXT: ret void314;315; GVN-LABEL: define amdgpu_kernel void @test6(316; GVN-SAME: i1 [[TMP0:%.*]], ptr addrspace(3) [[TMP1:%.*]]) {317; GVN-NEXT: [[ENTRY:.*:]]318; GVN-NEXT: [[TMP2:%.*]] = select i1 [[TMP0]], i32 0, i32 288319; GVN-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 32320; GVN-NEXT: [[TMP4:%.*]] = add i32 [[TMP2]], 256321; GVN-NEXT: [[TMP5:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP3]]322; GVN-NEXT: [[TMP6:%.*]] = xor i32 [[TMP4]], 32323; GVN-NEXT: [[TMP7:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP6]]324; GVN-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP7]], i32 8192325; GVN-NEXT: [[TMP9:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP5]], align 16326; GVN-NEXT: [[TMP10:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP8]], align 16327; GVN-NEXT: [[TMP11:%.*]] = fadd <8 x half> [[TMP9]], [[TMP10]]328; GVN-NEXT: store <8 x half> [[TMP11]], ptr addrspace(3) [[TMP1]], align 16329; GVN-NEXT: ret void330;331entry:332 %2 = select i1 %0, i32 0, i32 288333 %3 = xor i32 %2, 32334 %4 = add i32 %2, 256335 %5 = xor i32 %4, 4128336 %6 = getelementptr half, ptr addrspace(3) %1, i32 %3337 %7 = getelementptr half, ptr addrspace(3) %1, i32 %5338 %8 = load <8 x half>, ptr addrspace(3) %6, align 16339 %9 = load <8 x half>, ptr addrspace(3) %7, align 16340 %10 = fadd <8 x half> %8, %9341 store <8 x half> %10, ptr addrspace(3) %1, align 16342 ret void343}344 345; Verify that BinOp-XOR-GEP usage chains with non disjoint xor works as346; intended.347define amdgpu_kernel void @test6a(i1 %0, ptr addrspace(3) %1) {348; CHECK-LABEL: define amdgpu_kernel void @test6a(349; CHECK-SAME: i1 [[TMP0:%.*]], ptr addrspace(3) [[TMP1:%.*]]) {350; CHECK-NEXT: [[ENTRY:.*:]]351; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP0]], i32 0, i32 288352; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 32353; CHECK-NEXT: [[TMP4:%.*]] = add i32 [[TMP2]], 256354; CHECK-NEXT: [[TMP5:%.*]] = xor i32 [[TMP4]], 288355; CHECK-NEXT: [[TMP6:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP3]]356; CHECK-NEXT: [[TMP7:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP5]]357; CHECK-NEXT: [[TMP8:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP6]], align 16358; CHECK-NEXT: [[TMP9:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP7]], align 16359; CHECK-NEXT: [[TMP10:%.*]] = fadd <8 x half> [[TMP8]], [[TMP9]]360; CHECK-NEXT: store <8 x half> [[TMP10]], ptr addrspace(3) [[TMP1]], align 16361; CHECK-NEXT: ret void362;363; GVN-LABEL: define amdgpu_kernel void @test6a(364; GVN-SAME: i1 [[TMP0:%.*]], ptr addrspace(3) [[TMP1:%.*]]) {365; GVN-NEXT: [[ENTRY:.*:]]366; GVN-NEXT: [[TMP2:%.*]] = select i1 [[TMP0]], i32 0, i32 288367; GVN-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 32368; GVN-NEXT: [[TMP4:%.*]] = add i32 [[TMP2]], 256369; GVN-NEXT: [[TMP5:%.*]] = xor i32 [[TMP4]], 288370; GVN-NEXT: [[TMP6:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP3]]371; GVN-NEXT: [[TMP7:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP5]]372; GVN-NEXT: [[TMP8:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP6]], align 16373; GVN-NEXT: [[TMP9:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP7]], align 16374; GVN-NEXT: [[TMP10:%.*]] = fadd <8 x half> [[TMP8]], [[TMP9]]375; GVN-NEXT: store <8 x half> [[TMP10]], ptr addrspace(3) [[TMP1]], align 16376; GVN-NEXT: ret void377;378entry:379 %2 = select i1 %0, i32 0, i32 288380 %3 = xor i32 %2, 32381 %4 = add i32 %2, 256382 %5 = xor i32 %4, 288383 %6 = getelementptr half, ptr addrspace(3) %1, i32 %3384 %7 = getelementptr half, ptr addrspace(3) %1, i32 %5385 %8 = load <8 x half>, ptr addrspace(3) %6, align 16386 %9 = load <8 x half>, ptr addrspace(3) %7, align 16387 %10 = fadd <8 x half> %8, %9388 store <8 x half> %10, ptr addrspace(3) %1, align 16389 ret void390}391 392; Ensure disjoint constants exceeding addressing mode limits (e.g., 32768) are393; not extracted394define amdgpu_kernel void @test7(i1 %0, ptr addrspace(3) %1) {395; CHECK-LABEL: define amdgpu_kernel void @test7(396; CHECK-SAME: i1 [[TMP0:%.*]], ptr addrspace(3) [[TMP1:%.*]]) {397; CHECK-NEXT: [[ENTRY:.*:]]398; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP0]], i32 0, i32 288399; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 32400; CHECK-NEXT: [[TMP4:%.*]] = xor i32 [[TMP2]], 32800401; CHECK-NEXT: [[TMP5:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP3]]402; CHECK-NEXT: [[TMP6:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP4]]403; CHECK-NEXT: [[TMP7:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP5]], align 16404; CHECK-NEXT: [[TMP8:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP6]], align 16405; CHECK-NEXT: [[TMP9:%.*]] = fadd <8 x half> [[TMP7]], [[TMP8]]406; CHECK-NEXT: store <8 x half> [[TMP9]], ptr addrspace(3) [[TMP1]], align 16407; CHECK-NEXT: ret void408;409; GVN-LABEL: define amdgpu_kernel void @test7(410; GVN-SAME: i1 [[TMP0:%.*]], ptr addrspace(3) [[TMP1:%.*]]) {411; GVN-NEXT: [[ENTRY:.*:]]412; GVN-NEXT: [[TMP2:%.*]] = select i1 [[TMP0]], i32 0, i32 288413; GVN-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 32414; GVN-NEXT: [[TMP4:%.*]] = xor i32 [[TMP2]], 32800415; GVN-NEXT: [[TMP5:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP3]]416; GVN-NEXT: [[TMP6:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP4]]417; GVN-NEXT: [[TMP7:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP5]], align 16418; GVN-NEXT: [[TMP8:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP6]], align 16419; GVN-NEXT: [[TMP9:%.*]] = fadd <8 x half> [[TMP7]], [[TMP8]]420; GVN-NEXT: store <8 x half> [[TMP9]], ptr addrspace(3) [[TMP1]], align 16421; GVN-NEXT: ret void422;423entry:424 %2 = select i1 %0, i32 0, i32 288425 %3 = xor i32 %2, 32426 %4 = xor i32 %2, 32800427 %5 = getelementptr half, ptr addrspace(3) %1, i32 %3428 %6 = getelementptr half, ptr addrspace(3) %1, i32 %4429 %7 = load <8 x half>, ptr addrspace(3) %5, align 16430 %8 = load <8 x half>, ptr addrspace(3) %6, align 16431 %9 = fadd <8 x half> %7, %8432 store <8 x half> %9, ptr addrspace(3) %1, align 16433 ret void434}435 436