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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -S -passes='print<scalar-evolution>,simple-loop-unswitch<nontrivial>,print<scalar-evolution>' -verify-scev < %s 2>/dev/null | FileCheck %s3 4; Make sure we don't assert due to insufficient SCEV invalidation.5 6define void @test(ptr %p) {7; CHECK-LABEL: define void @test(8; CHECK-SAME: ptr [[P:%.*]]) {9; CHECK-NEXT: [[ENTRY:.*:]]10; CHECK-NEXT: [[CHECK:%.*]] = icmp eq ptr [[P]], null11; CHECK-NEXT: br i1 [[CHECK]], label %[[ENTRY_SPLIT_US:.*]], label %[[ENTRY_SPLIT:.*]]12; CHECK: [[ENTRY_SPLIT_US]]:13; CHECK-NEXT: br label %[[BB0_US:.*]]14; CHECK: [[BB0_US]]:15; CHECK-NEXT: br label %[[LOOP0_US:.*]]16; CHECK: [[LOOP0_US]]:17; CHECK-NEXT: [[V_US:%.*]] = load atomic i32, ptr [[P]] unordered, align 818; CHECK-NEXT: [[ADD_US:%.*]] = add i32 [[V_US]], 319; CHECK-NEXT: br i1 true, label %[[PREHEADER_SPLIT_US:.*]], label %[[BB0_US]]20; CHECK: [[PREHEADER_SPLIT_US]]:21; CHECK-NEXT: [[ADD_LCSSA_US:%.*]] = phi i32 [ [[ADD_US]], %[[LOOP0_US]] ]22; CHECK-NEXT: br label %[[PREHEADER:.*]]23; CHECK: [[ENTRY_SPLIT]]:24; CHECK-NEXT: br label %[[BB0:.*]]25; CHECK: [[BB0]]:26; CHECK-NEXT: br label %[[LATCH:.*]]27; CHECK: [[LATCH]]:28; CHECK-NEXT: br i1 false, label %[[EXIT0:.*]], label %[[LOOP0:.*]]29; CHECK: [[EXIT0]]:30; CHECK-NEXT: ret void31; CHECK: [[LOOP0]]:32; CHECK-NEXT: [[V:%.*]] = load atomic i32, ptr [[P]] unordered, align 833; CHECK-NEXT: [[ADD:%.*]] = add i32 [[V]], 334; CHECK-NEXT: br i1 true, label %[[PREHEADER_SPLIT:.*]], label %[[BB0]]35; CHECK: [[PREHEADER_SPLIT]]:36; CHECK-NEXT: [[ADD_LCSSA:%.*]] = phi i32 [ [[ADD]], %[[LOOP0]] ]37; CHECK-NEXT: br label %[[PREHEADER]]38; CHECK: [[PREHEADER]]:39; CHECK-NEXT: [[DOTUS_PHI:%.*]] = phi i32 [ [[ADD_LCSSA]], %[[PREHEADER_SPLIT]] ], [ [[ADD_LCSSA_US]], %[[PREHEADER_SPLIT_US]] ]40; CHECK-NEXT: br label %[[LOOP1:.*]]41; CHECK: [[LOOP1]]:42; CHECK-NEXT: [[IV1:%.*]] = phi i32 [ [[DOTUS_PHI]], %[[PREHEADER]] ], [ [[IV1_NEXT:%.*]], %[[BACKEDGE:.*]] ]43; CHECK-NEXT: [[IV1_NEXT]] = add i32 [[IV1]], -3344; CHECK-NEXT: br label %[[LOOP2:.*]]45; CHECK: [[BACKEDGE]]:46; CHECK-NEXT: br i1 true, label %[[EXIT1:.*]], label %[[LOOP1]]47; CHECK: [[LOOP2]]:48; CHECK-NEXT: [[IV0:%.*]] = phi i32 [ [[IV1]], %[[LOOP1]] ], [ [[IV0_NEXT:%.*]], %[[LOOP2]] ]49; CHECK-NEXT: [[IV0_NEXT]] = add nsw i32 [[IV0]], 150; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[IV0_NEXT]], 051; CHECK-NEXT: br i1 [[CMP]], label %[[BACKEDGE]], label %[[LOOP2]]52; CHECK: [[EXIT1]]:53; CHECK-NEXT: ret void54;55entry:56 %check = icmp eq ptr %p, null57 br label %bb058 59bb0: ; preds = %loop0, %entry60 br i1 %check, label %loop0, label %latch61 62latch: ; preds = %bb063 br i1 %check, label %exit0, label %loop064 65exit0: ; preds = %latch66 ret void67 68loop0: ; preds = %latch, %bb069 %v = load atomic i32, ptr %p unordered, align 870 %add = add i32 %v, 371 br i1 true, label %preheader, label %bb072 73preheader: ; preds = %loop074 br label %loop175 76loop1: ; preds = %backedge, %preheader77 %iv1 = phi i32 [ %add, %preheader ], [ %iv1.next, %backedge ]78 %iv1.next = add i32 %iv1, -3379 br label %loop280 81backedge: ; preds = %loop282 br i1 true, label %exit1, label %loop183 84loop2: ; preds = %loop2, %loop185 %iv0 = phi i32 [ %iv1, %loop1 ], [ %iv0.next, %loop2 ]86 %iv0.next = add nsw i32 %iv0, 187 %cmp = icmp sgt i32 %iv0.next, 088 br i1 %cmp, label %backedge, label %loop289 90exit1: ; preds = %backedge91 ret void92}93