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1; RUN: opt -mtriple=x86_64-unknown-linux-gnu -vector-library=SVML -passes=inject-tli-mappings -S < %s | FileCheck %s --check-prefixes=COMMON,SVML2; RUN: opt -mtriple=x86_64-unknown-linux-gnu -vector-library=AMDLIBM -passes=inject-tli-mappings -S < %s | FileCheck %s --check-prefixes=COMMON,AMDLIBM3; RUN: opt -mtriple=powerpc64-unknown-linux-gnu -vector-library=MASSV -passes=inject-tli-mappings -S < %s | FileCheck %s --check-prefixes=COMMON,MASSV4; RUN: opt -mtriple=aarch64-unknown-linux-gnu -vector-library=LIBMVEC -passes=inject-tli-mappings -S < %s | FileCheck %s --check-prefixes=COMMON,LIBMVEC-AARCH645; RUN: opt -mtriple=x86_64-unknown-linux-gnu -vector-library=LIBMVEC -passes=inject-tli-mappings -S < %s | FileCheck %s --check-prefixes=COMMON,LIBMVEC-X866; RUN: opt -mtriple=x86_64-unknown-linux-gnu -vector-library=Accelerate -passes=inject-tli-mappings -S < %s | FileCheck %s --check-prefixes=COMMON,ACCELERATE7; RUN: opt -mtriple=aarch64-unknown-linux-gnu -vector-library=sleefgnuabi -passes=inject-tli-mappings -S < %s | FileCheck %s --check-prefixes=COMMON,SLEEFGNUABI8; RUN: opt -mtriple=riscv64-unknown-linux-gnu -vector-library=sleefgnuabi -passes=inject-tli-mappings -S < %s | FileCheck %s --check-prefixes=COMMON,SLEEFGNUABI_RISCV9; RUN: opt -mtriple=aarch64-unknown-linux-gnu -vector-library=ArmPL -passes=inject-tli-mappings -S < %s | FileCheck %s --check-prefixes=COMMON,ARMPL10 11; COMMON-LABEL: @llvm.compiler.used = appending global12; SVML-SAME: [6 x ptr] [13; SVML-SAME: ptr @__svml_sin2,14; SVML-SAME: ptr @__svml_sin4,15; SVML-SAME: ptr @__svml_sin8,16; SVML-SAME: ptr @__svml_log10f4,17; SVML-SAME: ptr @__svml_log10f8,18; SVML-SAME: ptr @__svml_log10f1619; AMDLIBM-SAME: [11 x ptr] [20; AMDLIBM-SAME: ptr @amd_vrd2_sin,21; AMDLIBM-SAME: ptr @amd_vrd4_sin,22; AMDLIBM-SAME: ptr @amd_vrd8_sin,23; AMDLIBM-SAME: ptr @amd_vrd4_sincos,24; AMDLIBM-SAME: ptr @amd_vrd8_sincos,25; AMDLIBM-SAME: ptr @amd_vrs4_sincosf,26; AMDLIBM-SAME: ptr @amd_vrs8_sincosf,27; AMDLIBM-SAME: ptr @amd_vrs16_sincosf28; AMDLIBM-SAME: ptr @amd_vrs4_log10f,29; AMDLIBM-SAME: ptr @amd_vrs8_log10f,30; AMDLIBM-SAME: ptr @amd_vrs16_log10f31; MASSV-SAME: [2 x ptr] [32; MASSV-SAME: ptr @__sind2,33; MASSV-SAME: ptr @__log10f434; ACCELERATE-SAME: [1 x ptr] [35; ACCELERATE-SAME: ptr @vlog10f36; LIBMVEC-AARCH64-SAME: [5 x ptr] [37; LIBMVEC-AARCH64-SAME: ptr @_ZGVnN2v_sin,38; LIBMVEC-AARCH64-SAME: ptr @_ZGVsMxv_sin,39; LIBMVEC-AARCH64-SAME: ptr @_ZGVnN2v_log10f,40; LIBMVEC-AARCH64-SAME: ptr @_ZGVnN4v_log10f,41; LIBMVEC-AARCH64-SAME: ptr @_ZGVsMxv_log10f42; LIBMVEC-X86-SAME: [2 x ptr] [43; LIBMVEC-X86-SAME: ptr @_ZGVbN2v_sin,44; LIBMVEC-X86-SAME: ptr @_ZGVdN4v_sin45; SLEEFGNUABI-SAME: [16 x ptr] [46; SLEEFGNUABI-SAME: ptr @_ZGVnN2vl8_modf,47; SLEEFGNUABI-SAME: ptr @_ZGVsNxvl8_modf,48; SLEEFGNUABI-SAME: ptr @_ZGVnN4vl4_modff,49; SLEEFGNUABI-SAME: ptr @_ZGVsNxvl4_modff,50; SLEEFGNUABI-SAME: ptr @_ZGVnN2v_sin,51; SLEEFGNUABI-SAME: ptr @_ZGVsMxv_sin,52; SLEEFGNUABI-SAME: ptr @_ZGVnN2vl8l8_sincos,53; SLEEFGNUABI-SAME: ptr @_ZGVsNxvl8l8_sincos,54; SLEEFGNUABI-SAME: ptr @_ZGVnN4vl4l4_sincosf,55; SLEEFGNUABI-SAME: ptr @_ZGVsNxvl4l4_sincosf,56; SLEEFGNUABI-SAME: ptr @_ZGVnN2vl8l8_sincospi,57; SLEEFGNUABI-SAME: ptr @_ZGVsNxvl8l8_sincospi,58; SLEEFGNUABI-SAME: ptr @_ZGVnN4vl4l4_sincospif,59; SLEEFGNUABI-SAME: ptr @_ZGVsNxvl4l4_sincospif,60; SLEEFGNUABI_SAME; ptr @_ZGVnN4v_log10f,61; SLEEFGNUABI-SAME: ptr @_ZGVsMxv_log10f62; ARMPL-SAME: [16 x ptr] [63; ARMPL-SAME: ptr @armpl_vmodfq_f64,64; ARMPL-SAME: ptr @armpl_svmodf_f64_x,65; ARMPL-SAME: ptr @armpl_vmodfq_f32,66; ARMPL-SAME: ptr @armpl_svmodf_f32_x,67; ARMPL-SAME: ptr @armpl_vsinq_f64,68; ARMPL-SAME: ptr @armpl_svsin_f64_x,69; ARMPL-SAME: ptr @armpl_vsincosq_f64,70; ARMPL-SAME: ptr @armpl_svsincos_f64_x,71; ARMPL-SAME: ptr @armpl_vsincosq_f32,72; ARMPL-SAME: ptr @armpl_svsincos_f32_x,73; ARMPL-SAME: ptr @armpl_vsincospiq_f64,74; ARMPL-SAME: ptr @armpl_svsincospi_f64_x,75; ARMPL-SAME: ptr @armpl_vsincospiq_f32,76; ARMPL-SAME: ptr @armpl_svsincospi_f32_x,77; ARMPL-SAME: ptr @armpl_vlog10q_f32,78; ARMPL-SAME: ptr @armpl_svlog10_f32_x79; COMMON-SAME: ], section "llvm.metadata"80 81define double @modf_f64(double %in, ptr %iptr) {82; COMMON-LABEL: @modf_f64(83; SLEEFGNUABI: call double @modf(double %{{.*}}, ptr %{{.*}}) #[[MODF:[0-9]+]]84; ARMPL: call double @modf(double %{{.*}}, ptr %{{.*}}) #[[MODF:[0-9]+]]85 %call = tail call double @modf(double %in, ptr %iptr)86 ret double %call87}88 89declare double @modf(double, ptr) #090 91define float @modf_f32(float %in, ptr %iptr) {92; COMMON-LABEL: @modf_f32(93; SLEEFGNUABI: call float @modff(float %{{.*}}, ptr %{{.*}}) #[[MODFF:[0-9]+]]94; ARMPL: call float @modff(float %{{.*}}, ptr %{{.*}}) #[[MODFF:[0-9]+]]95 %call = tail call float @modff(float %in, ptr %iptr)96 ret float %call97}98 99declare float @modff(float, ptr) #0100 101define double @sin_f64(double %in) {102; COMMON-LABEL: @sin_f64(103; SVML: call double @sin(double %{{.*}}) #[[SIN:[0-9]+]]104; AMDLIBM: call double @sin(double %{{.*}}) #[[SIN:[0-9]+]]105; MASSV: call double @sin(double %{{.*}}) #[[SIN:[0-9]+]]106; ACCELERATE: call double @sin(double %{{.*}})107; LIBMVEC-AARCH64: call double @sin(double %{{.*}}) #[[SIN:[0-9]+]]108; LIBMVEC-X86: call double @sin(double %{{.*}}) #[[SIN:[0-9]+]]109; SLEEFGNUABI: call double @sin(double %{{.*}}) #[[SIN:[0-9]+]]110; SLEEFGNUABI_RISCV: call double @sin(double %{{.*}}) #[[SIN:[0-9]+]]111; ARMPL: call double @sin(double %{{.*}}) #[[SIN:[0-9]+]]112; No mapping of "sin" to a vector function for Accelerate.113; ACCELERATE-NOT: _ZGV_LLVM_{{.*}}_sin({{.*}})114 %call = tail call double @sin(double %in)115 ret double %call116}117 118declare double @sin(double) #0119 120define void @sincos_f64(double %in, ptr %sin, ptr %cos) {121; COMMON-LABEL: @sincos_f64(122; SLEEFGNUABI: call void @sincos(double %{{.*}}, ptr %{{.*}}, ptr %{{.*}}) #[[SINCOS:[0-9]+]]123; ARMPL: call void @sincos(double %{{.*}}, ptr %{{.*}}, ptr %{{.*}}) #[[SINCOS:[0-9]+]]124; AMDLIBM: call void @sincos(double %{{.*}}, ptr %{{.*}}, ptr %{{.*}}) #[[SINCOS:[0-9]+]]125 call void @sincos(double %in, ptr %sin, ptr %cos)126 ret void127}128 129declare void @sincos(double, ptr, ptr) #0130 131define void @sincos_f32(float %in, ptr %sin, ptr %cos) {132; COMMON-LABEL: @sincos_f32(133; SLEEFGNUABI: call void @sincosf(float %{{.*}}, ptr %{{.*}}, ptr %{{.*}}) #[[SINCOSF:[0-9]+]]134; ARMPL: call void @sincosf(float %{{.*}}, ptr %{{.*}}, ptr %{{.*}}) #[[SINCOSF:[0-9]+]]135; AMDLIBM: call void @sincosf(float %{{.*}}, ptr %{{.*}}, ptr %{{.*}}) #[[SINCOSF:[0-9]+]]136 call void @sincosf(float %in, ptr %sin, ptr %cos)137 ret void138}139 140declare void @sincosf(float, ptr, ptr) #0141 142define void @sincospi_f64(double %in, ptr %sin, ptr %cos) {143; COMMON-LABEL: @sincospi_f64(144; SLEEFGNUABI: call void @sincospi(double %{{.*}}, ptr %{{.*}}, ptr %{{.*}}) #[[SINCOSPI:[0-9]+]]145; ARMPL: call void @sincospi(double %{{.*}}, ptr %{{.*}}, ptr %{{.*}}) #[[SINCOSPI:[0-9]+]]146 call void @sincospi(double %in, ptr %sin, ptr %cos)147 ret void148}149 150declare void @sincospi(double, ptr, ptr) #0151 152define void @sincospi_f32(float %in, ptr %sin, ptr %cos) {153; COMMON-LABEL: @sincospi_f32(154; SLEEFGNUABI: call void @sincospif(float %{{.*}}, ptr %{{.*}}, ptr %{{.*}}) #[[SINCOSPIF:[0-9]+]]155; ARMPL: call void @sincospif(float %{{.*}}, ptr %{{.*}}, ptr %{{.*}}) #[[SINCOSPIF:[0-9]+]]156 call void @sincospif(float %in, ptr %sin, ptr %cos)157 ret void158}159 160declare void @sincospif(float, ptr, ptr) #0161 162define float @call_llvm.log10.f32(float %in) {163; COMMON-LABEL: @call_llvm.log10.f32(164; SVML: call float @llvm.log10.f32(float %{{.*}})165; AMDLIBM: call float @llvm.log10.f32(float %{{.*}}) #[[LOG10:[0-9]+]]166; LIBMVEC-AARCH64: call float @llvm.log10.f32(float %{{.*}}) #[[LOG10:[0-9]+]]167; LIBMVEC-X86: call float @llvm.log10.f32(float %{{.*}})168; MASSV: call float @llvm.log10.f32(float %{{.*}}) #[[LOG10:[0-9]+]]169; ACCELERATE: call float @llvm.log10.f32(float %{{.*}}) #[[LOG10:[0-9]+]]170; SLEEFGNUABI: call float @llvm.log10.f32(float %{{.*}}) #[[LOG10:[0-9]+]]171; SLEEFGNUABI_RISCV: call float @llvm.log10.f32(float %{{.*}}) #[[LOG10:[0-9]+]]172; ARMPL: call float @llvm.log10.f32(float %{{.*}}) #[[LOG10:[0-9]+]]173; No mapping of "llvm.log10.f32" to a vector function for SVML.174; SVML-NOT: _ZGV_LLVM_{{.*}}_llvm.log10.f32({{.*}})175; AMDLIBM-NOT: _ZGV_LLVM_{{.*}}_llvm.log10.f32({{.*}})176; LIBMVEC-AARCH64-NOT: _ZGV_LLVM_{{.*}}_llvm.log10.f32({{.*}})177; LIBMVEC-X86-NOT: _ZGV_LLVM_{{.*}}_llvm.log10.f32({{.*}})178 %call = tail call float @llvm.log10.f32(float %in)179 ret float %call180}181 182declare float @llvm.log10.f32(float) #0183 184; SVML: declare <2 x double> @__svml_sin2(<2 x double>)185; SVML: declare <4 x double> @__svml_sin4(<4 x double>)186; SVML: declare <8 x double> @__svml_sin8(<8 x double>)187; SVML: declare <4 x float> @__svml_log10f4(<4 x float>)188; SVML: declare <8 x float> @__svml_log10f8(<8 x float>)189; SVML: declare <16 x float> @__svml_log10f16(<16 x float>)190 191; AMDLIBM: declare <2 x double> @amd_vrd2_sin(<2 x double>)192; AMDLIBM: declare <4 x double> @amd_vrd4_sin(<4 x double>)193; AMDLIBM: declare <8 x double> @amd_vrd8_sin(<8 x double>)194; AMDLIBM: declare void @amd_vrd4_sincos(<4 x double>, ptr, ptr)195; AMDLIBM: declare void @amd_vrd8_sincos(<8 x double>, ptr, ptr)196; AMDLIBM: declare void @amd_vrs4_sincosf(<4 x float>, ptr, ptr)197; AMDLIBM: declare void @amd_vrs8_sincosf(<8 x float>, ptr, ptr)198; AMDLIBM: declare void @amd_vrs16_sincosf(<16 x float>, ptr, ptr)199; AMDLIBM: declare <4 x float> @amd_vrs4_log10f(<4 x float>)200; AMDLIBM: declare <8 x float> @amd_vrs8_log10f(<8 x float>)201; AMDLIBM: declare <16 x float> @amd_vrs16_log10f(<16 x float>)202 203; MASSV: declare <2 x double> @__sind2(<2 x double>)204; MASSV: declare <4 x float> @__log10f4(<4 x float>)205 206; LIBMVEC-AARCH64: declare aarch64_vector_pcs <2 x double> @_ZGVnN2v_sin(<2 x double>)207; LIBMVEC-AARCH64: declare <vscale x 2 x double> @_ZGVsMxv_sin(<vscale x 2 x double>, <vscale x 2 x i1>)208; LIBMVEC-AARCH64: declare aarch64_vector_pcs <2 x float> @_ZGVnN2v_log10f(<2 x float>)209; LIBMVEC-AARCH64: declare aarch64_vector_pcs <4 x float> @_ZGVnN4v_log10f(<4 x float>)210; LIBMVEC-AARCH64: declare <vscale x 4 x float> @_ZGVsMxv_log10f(<vscale x 4 x float>, <vscale x 4 x i1>)211 212; LIBMVEC-X86: declare <2 x double> @_ZGVbN2v_sin(<2 x double>)213; LIBMVEC-X86: declare <4 x double> @_ZGVdN4v_sin(<4 x double>)214 215; ACCELERATE: declare <4 x float> @vlog10f(<4 x float>)216 217; SLEEFGNUABI: declare <2 x double> @_ZGVnN2vl8_modf(<2 x double>, ptr)218; SLEEFGNUABI: declare <vscale x 2 x double> @_ZGVsNxvl8_modf(<vscale x 2 x double>, ptr)219; SLEEFGNUABI: declare <4 x float> @_ZGVnN4vl4_modff(<4 x float>, ptr)220; SLEEFGNUABI: declare <vscale x 4 x float> @_ZGVsNxvl4_modff(<vscale x 4 x float>, ptr)221; SLEEFGNUABI: declare <2 x double> @_ZGVnN2v_sin(<2 x double>)222; SLEEFGNUABI: declare <vscale x 2 x double> @_ZGVsMxv_sin(<vscale x 2 x double>, <vscale x 2 x i1>)223; SLEEFGNUABI: declare void @_ZGVnN2vl8l8_sincos(<2 x double>, ptr, ptr)224; SLEEFGNUABI: declare void @_ZGVsNxvl8l8_sincos(<vscale x 2 x double>, ptr, ptr)225; SLEEFGNUABI: declare void @_ZGVnN4vl4l4_sincosf(<4 x float>, ptr, ptr)226; SLEEFGNUABI: declare void @_ZGVsNxvl4l4_sincosf(<vscale x 4 x float>, ptr, ptr)227; SLEEFGNUABI: declare void @_ZGVnN2vl8l8_sincospi(<2 x double>, ptr, ptr)228; SLEEFGNUABI: declare void @_ZGVsNxvl8l8_sincospi(<vscale x 2 x double>, ptr, ptr)229; SLEEFGNUABI: declare void @_ZGVnN4vl4l4_sincospif(<4 x float>, ptr, ptr)230; SLEEFGNUABI: declare void @_ZGVsNxvl4l4_sincospif(<vscale x 4 x float>, ptr, ptr)231; SLEEFGNUABI: declare <4 x float> @_ZGVnN4v_log10f(<4 x float>)232; SLEEFGNUABI: declare <vscale x 4 x float> @_ZGVsMxv_log10f(<vscale x 4 x float>, <vscale x 4 x i1>)233 234; SLEEFGNUABI_RISCV: declare <vscale x 2 x double> @Sleef_sindx_u10rvvm2(<vscale x 2 x double>)235; SLEEFGNUABI_RISCV: declare <vscale x 4 x float> @Sleef_log10fx_u10rvvm2(<vscale x 4 x float>)236 237; ARMPL: declare aarch64_vector_pcs <2 x double> @armpl_vmodfq_f64(<2 x double>, ptr)238; ARMPL: declare <vscale x 2 x double> @armpl_svmodf_f64_x(<vscale x 2 x double>, ptr, <vscale x 2 x i1>)239; ARMPL: declare aarch64_vector_pcs <4 x float> @armpl_vmodfq_f32(<4 x float>, ptr)240; ARMPL: declare <vscale x 4 x float> @armpl_svmodf_f32_x(<vscale x 4 x float>, ptr, <vscale x 4 x i1>)241; ARMPL: declare aarch64_vector_pcs <2 x double> @armpl_vsinq_f64(<2 x double>)242; ARMPL: declare <vscale x 2 x double> @armpl_svsin_f64_x(<vscale x 2 x double>, <vscale x 2 x i1>)243; ARMPL: declare aarch64_vector_pcs void @armpl_vsincosq_f64(<2 x double>, ptr, ptr)244; ARMPL: declare void @armpl_svsincos_f64_x(<vscale x 2 x double>, ptr, ptr, <vscale x 2 x i1>)245; ARMPL: declare aarch64_vector_pcs void @armpl_vsincosq_f32(<4 x float>, ptr, ptr)246; ARMPL: declare void @armpl_svsincos_f32_x(<vscale x 4 x float>, ptr, ptr, <vscale x 4 x i1>)247; ARMPL: declare aarch64_vector_pcs void @armpl_vsincospiq_f64(<2 x double>, ptr, ptr)248; ARMPL: declare void @armpl_svsincospi_f64_x(<vscale x 2 x double>, ptr, ptr, <vscale x 2 x i1>)249; ARMPL: declare aarch64_vector_pcs void @armpl_vsincospiq_f32(<4 x float>, ptr, ptr)250; ARMPL: declare void @armpl_svsincospi_f32_x(<vscale x 4 x float>, ptr, ptr, <vscale x 4 x i1>)251; ARMPL: declare aarch64_vector_pcs <4 x float> @armpl_vlog10q_f32(<4 x float>)252; ARMPL: declare <vscale x 4 x float> @armpl_svlog10_f32_x(<vscale x 4 x float>, <vscale x 4 x i1>)253 254attributes #0 = { nounwind readnone }255 256; SVML: attributes #[[SIN]] = { "vector-function-abi-variant"=257; SVML-SAME: "_ZGV_LLVM_N2v_sin(__svml_sin2),258; SVML-SAME: _ZGV_LLVM_N4v_sin(__svml_sin4),259; SVML-SAME: _ZGV_LLVM_N8v_sin(__svml_sin8)" }260 261; AMDLIBM: attributes #[[SIN]] = { "vector-function-abi-variant"=262; AMDLIBM-SAME: "_ZGV_LLVM_N2v_sin(amd_vrd2_sin),263; AMDLIBM-SAME: _ZGV_LLVM_N4v_sin(amd_vrd4_sin),264; AMDLIBM-SAME: _ZGV_LLVM_N8v_sin(amd_vrd8_sin)" }265; AMDLIBM: attributes #[[SINCOS]] = { "vector-function-abi-variant"=266; AMDLIBM-SAME: "_ZGV_LLVM_N4vl8l8_sincos(amd_vrd4_sincos),267; AMDLIBM-SAME: _ZGV_LLVM_N8vl8l8_sincos(amd_vrd8_sincos)" }268; AMDLIBM: attributes #[[SINCOSF]] = { "vector-function-abi-variant"=269; AMDLIBM-SAME: "_ZGV_LLVM_N4vl4l4_sincosf(amd_vrs4_sincosf),270; AMDLIBM-SAME: _ZGV_LLVM_N8vl4l4_sincosf(amd_vrs8_sincosf),271; AMDLIBM-SAME: _ZGV_LLVM_N16vl4l4_sincosf(amd_vrs16_sincosf)" }272; AMDLIBM: attributes #[[LOG10]] = { "vector-function-abi-variant"=273; AMDLIBM-SAME: "_ZGV_LLVM_N4v_llvm.log10.f32(amd_vrs4_log10f),274; AMDLIBM-SAME: _ZGV_LLVM_N8v_llvm.log10.f32(amd_vrs8_log10f),275; AMDLIBM-SAME: _ZGV_LLVM_N16v_llvm.log10.f32(amd_vrs16_log10f)" }276 277; MASSV: attributes #[[SIN]] = { "vector-function-abi-variant"=278; MASSV-SAME: "_ZGV_LLVM_N2v_sin(__sind2)" }279; MASSV: attributes #[[LOG10]] = { "vector-function-abi-variant"=280; MASSV-SAME: "_ZGV_LLVM_N4v_llvm.log10.f32(__log10f4)" }281 282; ACCELERATE: attributes #[[LOG10]] = { "vector-function-abi-variant"=283; ACCELERATE-SAME: "_ZGV_LLVM_N4v_llvm.log10.f32(vlog10f)" }284 285; LIBMVEC-AARCH64: attributes #[[SIN]] = { "vector-function-abi-variant"=286; LIBMVEC-AARCH64-SAME: "_ZGV_LLVM_N2v_sin(_ZGVnN2v_sin),287; LIBMVEC-AARCH64-SAME: _ZGVsMxv_sin(_ZGVsMxv_sin)" }288; LIBMVEC-AARCH64: attributes #[[LOG10]] = { "vector-function-abi-variant"=289; LIBMVEC-AARCH64-SAME: "_ZGV_LLVM_N2v_llvm.log10.f32(_ZGVnN2v_log10f),290; LIBMVEC-AARCH64-SAME: _ZGV_LLVM_N4v_llvm.log10.f32(_ZGVnN4v_log10f),291; LIBMVEC-AARCH64-SAME: _ZGVsMxv_llvm.log10.f32(_ZGVsMxv_log10f)" }292 293; LIBMVEC-X86: attributes #[[SIN]] = { "vector-function-abi-variant"=294; LIBMVEC-X86-SAME: "_ZGV_LLVM_N2v_sin(_ZGVbN2v_sin),295; LIBMVEC-X86-SAME: _ZGV_LLVM_N4v_sin(_ZGVdN4v_sin)" }296 297; SLEEFGNUABI: attributes #[[MODF]] = { "vector-function-abi-variant"=298; SLEEFGNUABI-SAME: "_ZGV_LLVM_N2vl8_modf(_ZGVnN2vl8_modf),299; SLEEFGNUABI-SAME: _ZGVsNxvl8_modf(_ZGVsNxvl8_modf)" }300; SLEEFGNUABI: attributes #[[MODFF]] = { "vector-function-abi-variant"=301; SLEEFGNUABI-SAME: "_ZGV_LLVM_N4vl4_modff(_ZGVnN4vl4_modff),302; SLEEFGNUABI-SAME: _ZGVsNxvl4_modff(_ZGVsNxvl4_modff)" }303; SLEEFGNUABI: attributes #[[SIN]] = { "vector-function-abi-variant"=304; SLEEFGNUABI-SAME: "_ZGV_LLVM_N2v_sin(_ZGVnN2v_sin),305; SLEEFGNUABI-SAME: _ZGVsMxv_sin(_ZGVsMxv_sin)" }306; SLEEFGNUABI: attributes #[[SINCOS]] = { "vector-function-abi-variant"=307; SLEEFGNUABI-SAME: "_ZGV_LLVM_N2vl8l8_sincos(_ZGVnN2vl8l8_sincos),308; SLEEFGNUABI-SAME: _ZGVsNxvl8l8_sincos(_ZGVsNxvl8l8_sincos)" }309; SLEEFGNUABI: attributes #[[SINCOSF]] = { "vector-function-abi-variant"=310; SLEEFGNUABI-SAME: "_ZGV_LLVM_N4vl4l4_sincosf(_ZGVnN4vl4l4_sincosf),311; SLEEFGNUABI-SAME: _ZGVsNxvl4l4_sincosf(_ZGVsNxvl4l4_sincosf)" }312; SLEEFGNUABI: attributes #[[SINCOSPI]] = { "vector-function-abi-variant"=313; SLEEFGNUABI-SAME: "_ZGV_LLVM_N2vl8l8_sincospi(_ZGVnN2vl8l8_sincospi),314; SLEEFGNUABI-SAME: _ZGVsNxvl8l8_sincospi(_ZGVsNxvl8l8_sincospi)" }315; SLEEFGNUABI: attributes #[[SINCOSPIF]] = { "vector-function-abi-variant"=316; SLEEFGNUABI-SAME: "_ZGV_LLVM_N4vl4l4_sincospif(_ZGVnN4vl4l4_sincospif),317; SLEEFGNUABI-SAME: _ZGVsNxvl4l4_sincospif(_ZGVsNxvl4l4_sincospif)" }318; SLEEFGNUABI: attributes #[[LOG10]] = { "vector-function-abi-variant"=319; SLEEFGNUABI-SAME: "_ZGV_LLVM_N4v_llvm.log10.f32(_ZGVnN4v_log10f),320; SLEEFGNUABI-SAME: _ZGVsMxv_llvm.log10.f32(_ZGVsMxv_log10f)" }321 322; SLEEFGNUABI_RISCV: attributes #[[SIN]] = { "vector-function-abi-variant"=323; SLEEFGNUABI_RISCV-SAME: "_ZGVrNxv_sin(Sleef_sindx_u10rvvm2)" }324; SLEEFGNUABI_RISCV: attributes #[[LOG10]] = { "vector-function-abi-variant"=325; SLEEFGNUABI_RISCV-SAME: "_ZGVrNxv_llvm.log10.f32(Sleef_log10fx_u10rvvm2)" }326 327; ARMPL: attributes #[[MODF]] = { "vector-function-abi-variant"=328; ARMPL-SAME: "_ZGV_LLVM_N2vl8_modf(armpl_vmodfq_f64),329; ARMPL-SAME: _ZGVsMxvl8_modf(armpl_svmodf_f64_x)" }330; ARMPL: attributes #[[MODFF]] = { "vector-function-abi-variant"=331; ARMPL-SAME: "_ZGV_LLVM_N4vl4_modff(armpl_vmodfq_f32),332; ARMPL-SAME: _ZGVsMxvl4_modff(armpl_svmodf_f32_x)" }333; ARMPL: attributes #[[SIN]] = { "vector-function-abi-variant"=334; ARMPL-SAME: "_ZGV_LLVM_N2v_sin(armpl_vsinq_f64),335; ARMPL-SAME: _ZGVsMxv_sin(armpl_svsin_f64_x)" }336; ARMPL: attributes #[[SINCOS]] = { "vector-function-abi-variant"=337; ARMPL-SAME: "_ZGV_LLVM_N2vl8l8_sincos(armpl_vsincosq_f64),338; ARMPL-SAME: _ZGVsMxvl8l8_sincos(armpl_svsincos_f64_x)" }339; ARMPL: attributes #[[SINCOSF]] = { "vector-function-abi-variant"=340; ARMPL-SAME: "_ZGV_LLVM_N4vl4l4_sincosf(armpl_vsincosq_f32),341; ARMPL-SAME: _ZGVsMxvl4l4_sincosf(armpl_svsincos_f32_x)" }342; ARMPL: attributes #[[SINCOSPI]] = { "vector-function-abi-variant"=343; ARMPL-SAME: "_ZGV_LLVM_N2vl8l8_sincospi(armpl_vsincospiq_f64),344; ARMPL-SAME: _ZGVsMxvl8l8_sincospi(armpl_svsincospi_f64_x)" }345; ARMPL: attributes #[[SINCOSPIF]] = { "vector-function-abi-variant"=346; ARMPL-SAME: "_ZGV_LLVM_N4vl4l4_sincospif(armpl_vsincospiq_f32),347; ARMPL-SAME: _ZGVsMxvl4l4_sincospif(armpl_svsincospi_f32_x)" }348; ARMPL: attributes #[[LOG10]] = { "vector-function-abi-variant"=349; ARMPL-SAME: "_ZGV_LLVM_N4v_llvm.log10.f32(armpl_vlog10q_f32),350; ARMPL-SAME: _ZGVsMxv_llvm.log10.f32(armpl_svlog10_f32_x)" }351