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1; RUN: not llvm-as %s -disable-output 2>&1 | FileCheck %s2 3declare void @llvm.amdgcn.cs.chain(ptr, i32, <4 x i32>, { ptr, <3 x i32> }, i32, ...) noreturn4declare i32 @llvm.amdgcn.set.inactive.chain.arg(i32, i32) convergent willreturn nofree nocallback readnone5 6define amdgpu_cs_chain void @bad_flags(ptr %fn, i32 %exec, <4 x i32> inreg %sgpr, { ptr, <3 x i32> } %vgpr, i32 %flags) {7 ; CHECK: immarg operand has non-immediate parameter8 ; CHECK-NEXT: i32 %flags9 ; CHECK-NEXT: @llvm.amdgcn.cs.chain10 call void(ptr, i32, <4 x i32>, { ptr, <3 x i32> }, i32, ...) @llvm.amdgcn.cs.chain(ptr %fn, i32 %exec, <4 x i32> %sgpr, { ptr, <3 x i32> } %vgpr, i32 %flags)11 unreachable12}13 14define amdgpu_cs_chain void @bad_vgpr_args(ptr %fn, i32 %exec, <4 x i32> inreg %sgpr, { ptr, <3 x i32> } inreg %vgpr) {15 ; CHECK: VGPR arguments must not have the `inreg` attribute16 ; CHECK-NEXT: @llvm.amdgcn.cs.chain17 call void(ptr, i32, <4 x i32>, { ptr, <3 x i32> }, i32, ...) @llvm.amdgcn.cs.chain(ptr %fn, i32 %exec, <4 x i32> inreg %sgpr, { ptr, <3 x i32> } inreg %vgpr, i32 0)18 unreachable19}20 21define amdgpu_cs_chain void @bad_sgpr_args(ptr %fn, i32 %exec, <4 x i32> %sgpr, { ptr, <3 x i32> } %vgpr) {22 ; CHECK: SGPR arguments must have the `inreg` attribute23 ; CHECK-NEXT: @llvm.amdgcn.cs.chain24 call void(ptr, i32, <4 x i32>, { ptr, <3 x i32> }, i32, ...) @llvm.amdgcn.cs.chain(ptr %fn, i32 %exec, <4 x i32> %sgpr, { ptr, <3 x i32> } %vgpr, i32 0)25 unreachable26}27 28define amdgpu_cs_chain void @bad_exec(ptr %fn, i32 %exec, <4 x i32> inreg %sgpr, { ptr, <3 x i32> } %vgpr, i32 %flags) {29 ; CHECK: Intrinsic called with incompatible signature30 ; CHECK-NEXT: @llvm.amdgcn.cs.chain31 call void(ptr, <4 x i32>, <4 x i32>, { ptr, <3 x i32> }, i32, ...) @llvm.amdgcn.cs.chain(ptr %fn, <4 x i32> %sgpr, <4 x i32> %sgpr, { ptr, <3 x i32> } %vgpr, i32 %flags)32 unreachable33}34 35define amdgpu_cs_chain void @not_unreachable(ptr %fn, i32 %exec, <4 x i32> inreg %sgpr, { ptr, <3 x i32> } %vgpr) {36 ; CHECK: llvm.amdgcn.cs.chain must be followed by unreachable37 ; CHECK-NEXT: @llvm.amdgcn.cs.chain38 call void(ptr, i32, <4 x i32>, { ptr, <3 x i32> }, i32, ...) @llvm.amdgcn.cs.chain(ptr %fn, i32 %exec, <4 x i32> inreg %sgpr, { ptr, <3 x i32> } %vgpr, i32 0)39 ret void40}41 42define void @bad_caller_default_cc(ptr %fn, i32 %exec, <4 x i32> inreg %sgpr, { ptr, <3 x i32> } %vgpr) {43 ; CHECK: Intrinsic can only be used from functions with the amdgpu_cs_chain or amdgpu_cs_chain_preserve calling conventions44 ; CHECK-NEXT: @llvm.amdgcn.set.inactive.chain.arg45 %unused = call i32 @llvm.amdgcn.set.inactive.chain.arg(i32 0, i32 1)46 47 ; CHECK: Intrinsic can only be used from functions with the amdgpu_cs, amdgpu_cs_chain or amdgpu_cs_chain_preserve calling conventions48 ; CHECK-NEXT: @llvm.amdgcn.cs.chain49 call void(ptr, i32, <4 x i32>, { ptr, <3 x i32> }, i32, ...) @llvm.amdgcn.cs.chain(ptr %fn, i32 %exec, <4 x i32> %sgpr, { ptr, <3 x i32> } %vgpr, i32 0)50 unreachable51}52 53define amdgpu_kernel void @bad_caller_amdgpu_kernel(ptr %fn, i32 %exec, <4 x i32> inreg %sgpr, { ptr, <3 x i32> } %vgpr) {54 ; CHECK: Intrinsic can only be used from functions with the amdgpu_cs_chain or amdgpu_cs_chain_preserve calling conventions55 ; CHECK-NEXT: @llvm.amdgcn.set.inactive.chain.arg56 %unused = call i32 @llvm.amdgcn.set.inactive.chain.arg(i32 0, i32 1)57 58 ; CHECK: Intrinsic can only be used from functions with the amdgpu_cs, amdgpu_cs_chain or amdgpu_cs_chain_preserve calling conventions59 ; CHECK-NEXT: @llvm.amdgcn.cs.chain60 call void(ptr, i32, <4 x i32>, { ptr, <3 x i32> }, i32, ...) @llvm.amdgcn.cs.chain(ptr %fn, i32 %exec, <4 x i32> %sgpr, { ptr, <3 x i32> } %vgpr, i32 0)61 unreachable62}63 64define amdgpu_gfx void @bad_caller_amdgpu_gfx(ptr %fn, i32 %exec, <4 x i32> inreg %sgpr, { ptr, <3 x i32> } %vgpr) {65 ; CHECK: Intrinsic can only be used from functions with the amdgpu_cs_chain or amdgpu_cs_chain_preserve calling conventions66 ; CHECK-NEXT: @llvm.amdgcn.set.inactive.chain.arg67 %unused = call i32 @llvm.amdgcn.set.inactive.chain.arg(i32 0, i32 1)68 69 ; CHECK: Intrinsic can only be used from functions with the amdgpu_cs, amdgpu_cs_chain or amdgpu_cs_chain_preserve calling conventions70 ; CHECK-NEXT: @llvm.amdgcn.cs.chain71 call void(ptr, i32, <4 x i32>, { ptr, <3 x i32> }, i32, ...) @llvm.amdgcn.cs.chain(ptr %fn, i32 %exec, <4 x i32> %sgpr, { ptr, <3 x i32> } %vgpr, i32 0)72 unreachable73}74 75define amdgpu_vs void @bad_caller_amdgpu_vs(ptr %fn, i32 %exec, <4 x i32> inreg %sgpr, { ptr, <3 x i32> } %vgpr) {76 ; CHECK: Intrinsic can only be used from functions with the amdgpu_cs_chain or amdgpu_cs_chain_preserve calling conventions77 ; CHECK-NEXT: @llvm.amdgcn.set.inactive.chain.arg78 %unused = call i32 @llvm.amdgcn.set.inactive.chain.arg(i32 0, i32 1)79 80 ; CHECK: Intrinsic can only be used from functions with the amdgpu_cs, amdgpu_cs_chain or amdgpu_cs_chain_preserve calling conventions81 ; CHECK-NEXT: @llvm.amdgcn.cs.chain82 call void(ptr, i32, <4 x i32>, { ptr, <3 x i32> }, i32, ...) @llvm.amdgcn.cs.chain(ptr %fn, i32 %exec, <4 x i32> %sgpr, { ptr, <3 x i32> } %vgpr, i32 0)83 unreachable84}85 86define amdgpu_cs void @bad_caller_amdgpu_cs(ptr %fn, i32 %exec, <4 x i32> inreg %sgpr, { ptr, <3 x i32> } %vgpr) {87 ; CHECK: Intrinsic can only be used from functions with the amdgpu_cs_chain or amdgpu_cs_chain_preserve calling conventions88 ; CHECK-NEXT: @llvm.amdgcn.set.inactive.chain.arg89 %unused = call i32 @llvm.amdgcn.set.inactive.chain.arg(i32 0, i32 1)90 91 ; Unlike llvm.amdgcn.set.inactive.chain.arg, llvm.amdgcn.cs.chain may be called from amdgpu_cs functions.92 93 ret void94}95 96define amdgpu_cs_chain void @set_inactive_chain_arg_sgpr(ptr addrspace(1) %out, i32 %active, i32 inreg %inactive) {97 ; CHECK: Value for inactive lanes must be a VGPR function argument98 ; CHECK-NEXT: @llvm.amdgcn.set.inactive.chain.arg99 %tmp = call i32 @llvm.amdgcn.set.inactive.chain.arg(i32 %active, i32 %inactive) #0100 store i32 %tmp, ptr addrspace(1) %out101 ret void102}103 104define amdgpu_cs_chain void @set_inactive_chain_arg_const(ptr addrspace(1) %out, i32 %active) {105 ; CHECK: Value for inactive lanes must be a function argument106 ; CHECK-NEXT: llvm.amdgcn.set.inactive.chain.arg107 %tmp = call i32 @llvm.amdgcn.set.inactive.chain.arg(i32 %active, i32 29) #0108 store i32 %tmp, ptr addrspace(1) %out109 ret void110}111 112define amdgpu_cs_chain void @set_inactive_chain_arg_computed(ptr addrspace(1) %out, i32 %active) {113 ; CHECK: Value for inactive lanes must be a function argument114 ; CHECK-NEXT: @llvm.amdgcn.set.inactive.chain.arg115 %inactive = add i32 %active, 127116 %tmp = call i32 @llvm.amdgcn.set.inactive.chain.arg(i32 %active, i32 %inactive) #0117 store i32 %tmp, ptr addrspace(1) %out118 ret void119}120 121define amdgpu_cs_chain void @set_inactive_chain_arg_inreg(ptr addrspace(1) %out, i32 %active, i32 %inactive) {122 ; CHECK: Value for inactive lanes must not have the `inreg` attribute123 ; CHECK-NEXT: @llvm.amdgcn.set.inactive.chain.arg124 %tmp = call i32 @llvm.amdgcn.set.inactive.chain.arg(i32 %active, i32 inreg %inactive) #0125 store i32 %tmp, ptr addrspace(1) %out126 ret void127}128