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1; RUN: not llvm-as %s -disable-output 2>&1 | FileCheck %s2 3declare float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32>, i32, i32, i32)4define void @raw_buffer_load_f32(<4 x i32> inreg %rsrc, i32 %ofs, i32 %sofs, i32 %arg) {5 ; CHECK: immarg operand has non-immediate parameter6 ; CHECK-NEXT: i32 %arg7 ; CHECK-NEXT: %data = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 %arg)8 %data = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 %arg)9 ret void10}11 12declare float @llvm.amdgcn.raw.buffer.load.format.f32(<4 x i32>, i32, i32, i32)13define void @raw_buffer_load_format_f32(<4 x i32> inreg %rsrc, i32 %ofs, i32 %sofs, i32 %arg) {14 ; CHECK: immarg operand has non-immediate parameter15 ; CHECK-NEXT: i32 %arg16 ; CHECK-NEXT: %data = call float @llvm.amdgcn.raw.buffer.load.format.f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 %arg)17 %data = call float @llvm.amdgcn.raw.buffer.load.format.f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 %arg)18 ret void19}20 21declare float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32>, i32, i32, i32, i32)22define void @struct_buffer_load_f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 %arg) {23 ; CHECK: immarg operand has non-immediate parameter24 ; CHECK-NEXT: i32 %arg25 ; CHECK-NEXT: %data = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 %arg)26 %data = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 %arg)27 ret void28}29 30declare float @llvm.amdgcn.struct.buffer.load.format.f32(<4 x i32>, i32, i32, i32, i32)31define void @struct_buffer_load_format_f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 %arg) {32 ; CHECK: immarg operand has non-immediate parameter33 ; CHECK-NEXT: i32 %arg34 ; CHECK-NEXT: %data = call float @llvm.amdgcn.struct.buffer.load.format.f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 %arg)35 %data = call float @llvm.amdgcn.struct.buffer.load.format.f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 %arg)36 ret void37}38 39declare <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32.v8i32.v4i32(i32, float, <8 x i32>, <4 x i32>, i1, i32, i32)40define void @invalid_image_sample_1d_v4f32_f32(float %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc, i32 %dmask, i1 %bool, i32 %arg) {41 ; CHECK: immarg operand has non-immediate parameter42 ; CHECK-NEXT: i32 %dmask43 ; CHECK-NEXT: %data0 = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32.v8i32.v4i32(i32 %dmask, float %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)44 %data0 = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32.v8i32.v4i32(i32 %dmask, float %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)45 46 ; CHECK: immarg operand has non-immediate parameter47 ; CHECK-NEXT: i1 %bool48 ; CHECK-NEXT: %data1 = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32.v8i32.v4i32(i32 0, float %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i1 %bool, i32 0, i32 0)49 %data1 = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32.v8i32.v4i32(i32 0, float %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i1 %bool, i32 0, i32 0)50 51 ; CHECK: immarg operand has non-immediate parameter52 ; CHECK-NEXT: i32 %arg53 ; CHECK-NEXT: %data2 = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32.v8i32.v4i32(i32 0, float %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 %arg, i32 0)54 %data2 = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32.v8i32.v4i32(i32 0, float %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 %arg, i32 0)55 56 ; CHECK: immarg operand has non-immediate parameter57 ; CHECK-NEXT: i32 %arg58 ; CHECK-NEXT: %data3 = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32.v8i32.v4i32(i32 0, float %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 %arg)59 %data3 = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32.v8i32.v4i32(i32 0, float %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 %arg)60 ret void61}62 63declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1)64define void @exp_invalid_inputs(i32 %tgt, i32 %en, i1 %bool) {65 ; CHECK: immarg operand has non-immediate parameter66 ; CHECK-NEXT: i32 %en67 ; CHECK-NEXT: call void @llvm.amdgcn.exp.f32(i32 0, i32 %en, float 1.000000e+00, float 2.000000e+00, float 5.000000e-01, float 4.000000e+00, i1 true, i1 false)68 call void @llvm.amdgcn.exp.f32(i32 0, i32 %en, float 1.0, float 2.0, float 0.5, float 4.0, i1 true, i1 false)69 70 ; CHECK: immarg operand has non-immediate parameter71 ; CHECK-NEXT: i32 %tgt72 ; CHECK-NEXT: call void @llvm.amdgcn.exp.f32(i32 %tgt, i32 15, float 1.000000e+00, float 2.000000e+00, float 5.000000e-01, float 4.000000e+00, i1 true, i1 false)73 call void @llvm.amdgcn.exp.f32(i32 %tgt, i32 15, float 1.0, float 2.0, float 0.5, float 4.0, i1 true, i1 false)74 75 ; CHECK: immarg operand has non-immediate parameter76 ; CHECK-NEXT: i1 %bool77 ; CHECK-NEXT: call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float 1.000000e+00, float 2.000000e+00, float 5.000000e-01, float 4.000000e+00, i1 %bool, i1 false)78 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float 1.0, float 2.0, float 0.5, float 4.0, i1 %bool, i1 false)79 80 ; CHECK: immarg operand has non-immediate parameter81 ; CHECK-NEXT: i1 %bool82 ; CHECK-NEXT: call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float 1.000000e+00, float 2.000000e+00, float 5.000000e-01, float 4.000000e+00, i1 false, i1 %bool)83 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float 1.0, float 2.0, float 0.5, float 4.0, i1 false, i1 %bool)84 ret void85}86 87declare void @llvm.amdgcn.exp.compr.v2f16(i32, i32, <2 x half>, <2 x half>, i1, i1)88 89define void @exp_compr_invalid_inputs(i32 %tgt, i32 %en, i1 %bool) {90 ; CHECK: immarg operand has non-immediate parameter91 ; CHECK-NEXT: i32 %en92 ; CHECK-NEXT: call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 %en, <2 x half> <half 0xH3C00, half 0xH4000>, <2 x half> <half 0xH3800, half 0xH4400>, i1 true, i1 false)93 call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 %en, <2 x half> <half 1.0, half 2.0>, <2 x half> <half 0.5, half 4.0>, i1 true, i1 false)94 95 ; CHECK: immarg operand has non-immediate parameter96 ; CHECK-NEXT: i32 %tgt97 ; CHECK-NEXT: call void @llvm.amdgcn.exp.compr.v2f16(i32 %tgt, i32 5, <2 x half> <half 0xH3C00, half 0xH4000>, <2 x half> <half 0xH3800, half 0xH4400>, i1 true, i1 false)98 call void @llvm.amdgcn.exp.compr.v2f16(i32 %tgt, i32 5, <2 x half> <half 1.0, half 2.0>, <2 x half> <half 0.5, half 4.0>, i1 true, i1 false)99 100 ; CHECK: immarg operand has non-immediate parameter101 ; CHECK-NEXT: i1 %bool102 ; CHECK-NEXT: call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 5, <2 x half> <half 0xH3C00, half 0xH4000>, <2 x half> <half 0xH3800, half 0xH4400>, i1 %bool, i1 false)103 call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 5, <2 x half> <half 1.0, half 2.0>, <2 x half> <half 0.5, half 4.0>, i1 %bool, i1 false)104 105 ; CHECK: immarg operand has non-immediate parameter106 ; CHECK-NEXT: i1 %bool107 ; CHECK-NEXT: call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 5, <2 x half> <half 0xH3C00, half 0xH4000>, <2 x half> <half 0xH3800, half 0xH4400>, i1 false, i1 %bool)108 call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 5, <2 x half> <half 1.0, half 2.0>, <2 x half> <half 0.5, half 4.0>, i1 false, i1 %bool)109 ret void110}111 112declare i64 @llvm.amdgcn.icmp.i64.i32(i32, i32, i32)113 114define i64 @invalid_nonconstant_icmp_code(i32 %a, i32 %b, i32 %c) {115 ; CHECK: immarg operand has non-immediate parameter116 ; CHECK-NEXT: i32 %c117 ; CHECK-NEXT: %result = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %a, i32 %b, i32 %c)118 %result = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %a, i32 %b, i32 %c)119 ret i64 %result120}121 122declare i64 @llvm.amdgcn.fcmp.i64.f32(float, float, i32)123define i64 @invalid_nonconstant_fcmp_code(float %a, float %b, i32 %c) {124 ; CHECK: immarg operand has non-immediate parameter125 ; CHECK-NEXT: i32 %c126 ; CHECK-NEXT: %result = call i64 @llvm.amdgcn.fcmp.i64.f32(float %a, float %b, i32 %c)127 %result = call i64 @llvm.amdgcn.fcmp.i64.f32(float %a, float %b, i32 %c)128 ret i64 %result129}130 131declare { float, i1 } @llvm.amdgcn.div.scale.f32(float, float, i1)132define amdgpu_kernel void @test_div_scale_f32_val_undef_undef(ptr addrspace(1) %out) {133 ; CHECK: immarg operand has non-immediate parameter134 ; CHECK: i1 undef135 ; CHECK: %result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float 8.000000e+00, float undef, i1 undef)136 %result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float 8.0, float undef, i1 undef)137 %result0 = extractvalue { float, i1 } %result, 0138 store float %result0, ptr addrspace(1) %out, align 4139 ret void140}141 142declare void @llvm.amdgcn.init.exec(i64)143define amdgpu_ps void @init_exec(i64 %var) {144 ; CHECK: immarg operand has non-immediate parameter145 ; CHECK-NEXT: i64 %var146 ; CHECK-NEXT: call void @llvm.amdgcn.init.exec(i64 %var)147 call void @llvm.amdgcn.init.exec(i64 %var)148 ret void149}150 151declare void @llvm.amdgcn.s.sendmsg(i32, i32)152define void @sendmsg(i32 %arg0, i32 %arg1) {153 ; CHECK: immarg operand has non-immediate parameter154 ; CHECK-NEXT: i32 %arg0155 ; CHECK-NEXT: call void @llvm.amdgcn.s.sendmsg(i32 %arg0, i32 %arg1)156 call void @llvm.amdgcn.s.sendmsg(i32 %arg0, i32 %arg1)157 ret void158}159 160declare void @llvm.amdgcn.s.sendmsghalt(i32, i32)161define void @sendmsghalt(i32 %arg0, i32 %arg1) {162 ; CHECK: immarg operand has non-immediate parameter163 ; CHECK-NEXT: i32 %arg0164 ; CHECK-NEXT: call void @llvm.amdgcn.s.sendmsghalt(i32 %arg0, i32 %arg1)165 call void @llvm.amdgcn.s.sendmsghalt(i32 %arg0, i32 %arg1)166 ret void167}168 169declare void @llvm.amdgcn.s.waitcnt(i32)170define void @waitcnt(i32 %arg0) {171 ; CHECK: immarg operand has non-immediate parameter172 ; CHECK-NEXT: i32 %arg0173 ; CHECK-NEXT: call void @llvm.amdgcn.s.waitcnt(i32 %arg0)174 call void @llvm.amdgcn.s.waitcnt(i32 %arg0)175 ret void176}177 178declare i32 @llvm.amdgcn.s.getreg(i32)179define void @getreg(i32 %arg0, i32 %arg1) {180 ; CHECK: immarg operand has non-immediate parameter181 ; CHECK-NEXT: i32 %arg0182 ; CHECK-NEXT: %val = call i32 @llvm.amdgcn.s.getreg(i32 %arg0)183 %val = call i32 @llvm.amdgcn.s.getreg(i32 %arg0)184 ret void185}186 187declare void @llvm.amdgcn.s.sleep(i32)188define void @sleep(i32 %arg0, i32 %arg1) {189 ; CHECK: immarg operand has non-immediate parameter190 ; CHECK-NEXT: i32 %arg0191 ; CHECK-NEXT: call void @llvm.amdgcn.s.sleep(i32 %arg0)192 call void @llvm.amdgcn.s.sleep(i32 %arg0)193 ret void194}195 196declare void @llvm.amdgcn.s.incperflevel(i32)197define void @incperflevel(i32 %arg0, i32 %arg1) {198 ; CHECK: immarg operand has non-immediate parameter199 ; CHECK-NEXT: i32 %arg0200 ; CHECK-NEXT: call void @llvm.amdgcn.s.incperflevel(i32 %arg0)201 call void @llvm.amdgcn.s.incperflevel(i32 %arg0)202 ret void203}204 205declare void @llvm.amdgcn.s.decperflevel(i32)206define void @decperflevel(i32 %arg0, i32 %arg1) {207 ; CHECK: immarg operand has non-immediate parameter208 ; CHECK-NEXT: i32 %arg0209 ; CHECK-NEXT: call void @llvm.amdgcn.s.decperflevel(i32 %arg0)210 call void @llvm.amdgcn.s.decperflevel(i32 %arg0)211 ret void212}213 214declare i32 @llvm.amdgcn.ds.swizzle(i32, i32)215define void @ds_swizzle(i32 %arg0, i32 %arg1) {216 ; CHECK: immarg operand has non-immediate parameter217 ; CHECK-NEXT: i32 %arg1218 ; CHECK-NEXT: %val = call i32 @llvm.amdgcn.ds.swizzle(i32 %arg0, i32 %arg1)219 %val = call i32 @llvm.amdgcn.ds.swizzle(i32 %arg0, i32 %arg1)220 ret void221}222 223declare i32 @llvm.amdgcn.ds.ordered.add(ptr addrspace(2) nocapture, i32, i32, i32, i1, i32, i1, i1)224define amdgpu_kernel void @ds_ordered_add(ptr addrspace(2) %gds, ptr addrspace(1) %out, i32 %var, i1 %bool) {225 ; CHECK: immarg operand has non-immediate parameter226 ; CHECK-NEXT: i32 %var227 ; CHECK-NEXT: %val0 = call i32 @llvm.amdgcn.ds.ordered.add(ptr addrspace(2) %gds, i32 31, i32 %var, i32 0, i1 false, i32 1, i1 true, i1 true)228 %val0 = call i32 @llvm.amdgcn.ds.ordered.add(ptr addrspace(2) %gds, i32 31, i32 %var, i32 0, i1 false, i32 1, i1 true, i1 true)229 230 ; CHECK: immarg operand has non-immediate parameter231 ; CHECK-NEXT: i32 %var232 ; CHECK-NEXT: %val1 = call i32 @llvm.amdgcn.ds.ordered.add(ptr addrspace(2) %gds, i32 31, i32 0, i32 %var, i1 false, i32 1, i1 true, i1 true)233 %val1 = call i32 @llvm.amdgcn.ds.ordered.add(ptr addrspace(2) %gds, i32 31, i32 0, i32 %var, i1 false, i32 1, i1 true, i1 true)234 235 ; CHECK: immarg operand has non-immediate parameter236 ; CHECK-NEXT: i1 %bool237 ; CHECK-NEXT: %val2 = call i32 @llvm.amdgcn.ds.ordered.add(ptr addrspace(2) %gds, i32 31, i32 0, i32 0, i1 %bool, i32 1, i1 true, i1 true)238 %val2 = call i32 @llvm.amdgcn.ds.ordered.add(ptr addrspace(2) %gds, i32 31, i32 0, i32 0, i1 %bool, i32 1, i1 true, i1 true)239 240 ; CHECK: immarg operand has non-immediate parameter241 ; CHECK-NEXT: i32 %var242 ; CHECK-NEXT: %val3 = call i32 @llvm.amdgcn.ds.ordered.add(ptr addrspace(2) %gds, i32 31, i32 0, i32 0, i1 false, i32 %var, i1 true, i1 true)243 %val3 = call i32 @llvm.amdgcn.ds.ordered.add(ptr addrspace(2) %gds, i32 31, i32 0, i32 0, i1 false, i32 %var, i1 true, i1 true)244 245 ; CHECK: immarg operand has non-immediate parameter246 ; CHECK-NEXT: i1 %bool247 ; CHECK-NEXT: %val4 = call i32 @llvm.amdgcn.ds.ordered.add(ptr addrspace(2) %gds, i32 31, i32 0, i32 0, i1 false, i32 1, i1 %bool, i1 true)248 %val4 = call i32 @llvm.amdgcn.ds.ordered.add(ptr addrspace(2) %gds, i32 31, i32 0, i32 0, i1 false, i32 1, i1 %bool, i1 true)249 250 ; CHECK: immarg operand has non-immediate parameter251 ; CHECK-NEXT: i1 %bool252 ; CHECK-NEXT: %val5 = call i32 @llvm.amdgcn.ds.ordered.add(ptr addrspace(2) %gds, i32 31, i32 0, i32 0, i1 false, i32 1, i1 true, i1 %bool)253 %val5 = call i32 @llvm.amdgcn.ds.ordered.add(ptr addrspace(2) %gds, i32 31, i32 0, i32 0, i1 false, i32 1, i1 true, i1 %bool)254 ret void255}256 257declare i32 @llvm.amdgcn.ds.ordered.swap(ptr addrspace(2) nocapture, i32, i32, i32, i1, i32, i1, i1)258define amdgpu_kernel void @ds_ordered_swap(ptr addrspace(2) %gds, ptr addrspace(1) %out, i32 %var, i1 %bool) {259 ; CHECK: immarg operand has non-immediate parameter260 ; CHECK-NEXT: i32 %var261 ; CHECK-NEXT: %val0 = call i32 @llvm.amdgcn.ds.ordered.swap(ptr addrspace(2) %gds, i32 31, i32 %var, i32 0, i1 false, i32 1, i1 true, i1 true)262 %val0 = call i32 @llvm.amdgcn.ds.ordered.swap(ptr addrspace(2) %gds, i32 31, i32 %var, i32 0, i1 false, i32 1, i1 true, i1 true)263 264 ; CHECK: immarg operand has non-immediate parameter265 ; CHECK-NEXT: i32 %var266 ; CHECK-NEXT: %val1 = call i32 @llvm.amdgcn.ds.ordered.swap(ptr addrspace(2) %gds, i32 31, i32 0, i32 %var, i1 false, i32 1, i1 true, i1 true)267 %val1 = call i32 @llvm.amdgcn.ds.ordered.swap(ptr addrspace(2) %gds, i32 31, i32 0, i32 %var, i1 false, i32 1, i1 true, i1 true)268 269 ; CHECK: immarg operand has non-immediate parameter270 ; CHECK-NEXT: i1 %bool271 ; CHECK-NEXT: %val2 = call i32 @llvm.amdgcn.ds.ordered.swap(ptr addrspace(2) %gds, i32 31, i32 0, i32 0, i1 %bool, i32 1, i1 true, i1 true)272 %val2 = call i32 @llvm.amdgcn.ds.ordered.swap(ptr addrspace(2) %gds, i32 31, i32 0, i32 0, i1 %bool, i32 1, i1 true, i1 true)273 274 ; CHECK: immarg operand has non-immediate parameter275 ; CHECK-NEXT: i32 %var276 ; CHECK-NEXT: %val3 = call i32 @llvm.amdgcn.ds.ordered.swap(ptr addrspace(2) %gds, i32 31, i32 0, i32 0, i1 false, i32 %var, i1 true, i1 true)277 %val3 = call i32 @llvm.amdgcn.ds.ordered.swap(ptr addrspace(2) %gds, i32 31, i32 0, i32 0, i1 false, i32 %var, i1 true, i1 true)278 279 ; CHECK: immarg operand has non-immediate parameter280 ; CHECK-NEXT: i1 %bool281 ; CHECK-NEXT: %val4 = call i32 @llvm.amdgcn.ds.ordered.swap(ptr addrspace(2) %gds, i32 31, i32 0, i32 0, i1 false, i32 1, i1 %bool, i1 true)282 %val4 = call i32 @llvm.amdgcn.ds.ordered.swap(ptr addrspace(2) %gds, i32 31, i32 0, i32 0, i1 false, i32 1, i1 %bool, i1 true)283 284 ; CHECK: immarg operand has non-immediate parameter285 ; CHECK-NEXT: i1 %bool286 ; CHECK-NEXT: %val5 = call i32 @llvm.amdgcn.ds.ordered.swap(ptr addrspace(2) %gds, i32 31, i32 0, i32 0, i1 false, i32 1, i1 true, i1 %bool)287 %val5 = call i32 @llvm.amdgcn.ds.ordered.swap(ptr addrspace(2) %gds, i32 31, i32 0, i32 0, i1 false, i32 1, i1 true, i1 %bool)288 ret void289}290 291declare i32 @llvm.amdgcn.mov.dpp.i32(i32, i32, i32, i32, i1)292define amdgpu_kernel void @mov_dpp_test(ptr addrspace(1) %out, i32 %in1, i32 %var, i1 %bool) {293 ; CHECK: immarg operand has non-immediate parameter294 ; CHECK-NEXT: i32 %var295 ; CHECK-NEXT: %val0 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %in1, i32 %var, i32 1, i32 1, i1 true)296 %val0 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %in1, i32 %var, i32 1, i32 1, i1 1)297 298 ; CHECK: immarg operand has non-immediate parameter299 ; CHECK-NEXT: i32 %var300 ; CHECK-NEXT: %val1 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %in1, i32 1, i32 %var, i32 1, i1 true)301 %val1 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %in1, i32 1, i32 %var, i32 1, i1 1)302 303 ; CHECK: immarg operand has non-immediate parameter304 ; CHECK-NEXT: i32 %var305 ; CHECK-NEXT: %val2 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %in1, i32 1, i32 1, i32 %var, i1 true)306 %val2 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %in1, i32 1, i32 1, i32 %var, i1 1)307 308 ; CHECK: immarg operand has non-immediate parameter309 ; CHECK-NEXT: i1 %bool310 ; CHECK-NEXT: %val3 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %in1, i32 1, i32 1, i32 1, i1 %bool)311 %val3 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %in1, i32 1, i32 1, i32 1, i1 %bool)312 ret void313}314 315declare i32 @llvm.amdgcn.update.dpp.i32(i32, i32, i32, i32, i32, i1)316define amdgpu_kernel void @update_dpp_test(ptr addrspace(1) %out, i32 %in1, i32 %in2, i32 %var, i1 %bool) {317 ; CHECK: immarg operand has non-immediate parameter318 ; CHECK-NEXT: i32 %var319 ; CHECK-NEXT: %val0 = call i32 @llvm.amdgcn.update.dpp.i32(i32 %in1, i32 %in2, i32 %var, i32 1, i32 1, i1 true)320 %val0 = call i32 @llvm.amdgcn.update.dpp.i32(i32 %in1, i32 %in2, i32 %var, i32 1, i32 1, i1 1)321 322 ; CHECK: immarg operand has non-immediate parameter323 ; CHECK-NEXT: i32 %var324 ; CHECK-NEXT: %val1 = call i32 @llvm.amdgcn.update.dpp.i32(i32 %in1, i32 %in2, i32 1, i32 %var, i32 1, i1 true)325 %val1 = call i32 @llvm.amdgcn.update.dpp.i32(i32 %in1, i32 %in2, i32 1, i32 %var, i32 1, i1 1)326 327 ; CHECK: immarg operand has non-immediate parameter328 ; CHECK-NEXT: i32 %var329 ; CHECK-NEXT: %val2 = call i32 @llvm.amdgcn.update.dpp.i32(i32 %in1, i32 %in2, i32 1, i32 1, i32 %var, i1 true)330 %val2 = call i32 @llvm.amdgcn.update.dpp.i32(i32 %in1, i32 %in2, i32 1, i32 1, i32 %var, i1 1)331 332 ; CHECK: immarg operand has non-immediate parameter333 ; CHECK-NEXT: i1 %bool334 ; CHECK-NEXT: %val3 = call i32 @llvm.amdgcn.update.dpp.i32(i32 %in1, i32 %in2, i32 1, i32 1, i32 1, i1 %bool)335 %val3 = call i32 @llvm.amdgcn.update.dpp.i32(i32 %in1, i32 %in2, i32 1, i32 1, i32 1, i1 %bool)336 ret void337}338 339declare <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32.v8i32(i32, i32, <8 x i32>, i32, i32)340define amdgpu_ps void @load_1d(<8 x i32> inreg %rsrc, i32 %s, i32 %var) {341 ; CHECK: immarg operand has non-immediate parameter342 ; CHECK-NEXT: i32 %var343 ; CHECK-NEXT: %val0 = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32.v8i32(i32 %var, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)344 %val0 = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32.v8i32(i32 %var, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)345 346 ; CHECK: immarg operand has non-immediate parameter347 ; CHECK-NEXT: i32 %var348 ; CHECK-NEXT: %val1 = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32.v8i32(i32 15, i32 %s, <8 x i32> %rsrc, i32 %var, i32 0)349 %val1 = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32.v8i32(i32 15, i32 %s, <8 x i32> %rsrc, i32 %var, i32 0)350 351 ; CHECK: immarg operand has non-immediate parameter352 ; CHECK-NEXT: i32 %var353 ; CHECK-NEXT: %val2 = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32.v8i32(i32 15, i32 %s, <8 x i32> %rsrc, i32 0, i32 %var)354 %val2 = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32.v8i32(i32 15, i32 %s, <8 x i32> %rsrc, i32 0, i32 %var)355 ret void356}357 358declare {<4 x float>,i32} @llvm.amdgcn.image.load.1d.v4f32i32.i32.v8i32(i32, i32, <8 x i32>, i32, i32)359define amdgpu_ps void @load_1d_tfe(<8 x i32> inreg %rsrc, ptr addrspace(1) inreg %out, i32 %s, i32 %val) {360 ; CHECK: immarg operand has non-immediate parameter361 ; CHECK-NEXT: i32 %val362 ; CHECK-NEXT: %val0 = call { <4 x float>, i32 } @llvm.amdgcn.image.load.1d.sl_v4f32i32s.i32.v8i32(i32 %val, i32 %s, <8 x i32> %rsrc, i32 1, i32 0)363 %val0 = call {<4 x float>, i32} @llvm.amdgcn.image.load.1d.v4f32i32.i32.v8i32(i32 %val, i32 %s, <8 x i32> %rsrc, i32 1, i32 0)364 365 ; CHECK: immarg operand has non-immediate parameter366 ; CHECK-NEXT: i32 %val367 ; CHECK-NEXT: %val1 = call { <4 x float>, i32 } @llvm.amdgcn.image.load.1d.sl_v4f32i32s.i32.v8i32(i32 15, i32 %s, <8 x i32> %rsrc, i32 %val, i32 0)368 %val1 = call {<4 x float>, i32} @llvm.amdgcn.image.load.1d.v4f32i32.i32.v8i32(i32 15, i32 %s, <8 x i32> %rsrc, i32 %val, i32 0)369 370 ; CHECK: immarg operand has non-immediate parameter371 ; CHECK-NEXT: i32 %val372 ; CHECK-NEXT: %val2 = call { <4 x float>, i32 } @llvm.amdgcn.image.load.1d.sl_v4f32i32s.i32.v8i32(i32 15, i32 %s, <8 x i32> %rsrc, i32 1, i32 %val)373 %val2 = call {<4 x float>, i32} @llvm.amdgcn.image.load.1d.v4f32i32.i32.v8i32(i32 15, i32 %s, <8 x i32> %rsrc, i32 1, i32 %val)374 ret void375}376 377declare {<4 x float>, i32} @llvm.amdgcn.image.sample.1d.v4f32i32.f32.v8i32.v4i32(i32, float, <8 x i32>, <4 x i32>, i1, i32, i32)378define amdgpu_ps void @sample_1d_tfe(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, ptr addrspace(1) inreg %out, float %s, i32 %var, i1 %bool) {379 ; CHECK: immarg operand has non-immediate parameter380 ; CHECK-NEXT: i32 %var381 ; CHECK-NEXT: %val0 = call { <4 x float>, i32 } @llvm.amdgcn.image.sample.1d.sl_v4f32i32s.f32.v8i32.v4i32(i32 %var, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 1, i32 0)382 %val0 = call {<4 x float>, i32} @llvm.amdgcn.image.sample.1d.v4f32i32.f32.v8i32.v4i32(i32 %var, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 1, i32 0)383 384 ; CHECK: immarg operand has non-immediate parameter385 ; CHECK-NEXT: i1 %bool386 ; CHECK-NEXT: %val1 = call { <4 x float>, i32 } @llvm.amdgcn.image.sample.1d.sl_v4f32i32s.f32.v8i32.v4i32(i32 16, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 %bool, i32 1, i32 0)387 %val1 = call {<4 x float>, i32} @llvm.amdgcn.image.sample.1d.v4f32i32.f32.v8i32.v4i32(i32 16, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 %bool, i32 1, i32 0)388 389 ; CHECK: immarg operand has non-immediate parameter390 ; CHECK-NEXT: i32 %var391 ; CHECK-NEXT: %val2 = call { <4 x float>, i32 } @llvm.amdgcn.image.sample.1d.sl_v4f32i32s.f32.v8i32.v4i32(i32 16, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 %var, i32 0)392 %val2 = call {<4 x float>, i32} @llvm.amdgcn.image.sample.1d.v4f32i32.f32.v8i32.v4i32(i32 16, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 %var, i32 0)393 394 ; CHECK: immarg operand has non-immediate parameter395 ; CHECK-NEXT: i32 %var396 ; CHECK-NEXT: %val3 = call { <4 x float>, i32 } @llvm.amdgcn.image.sample.1d.sl_v4f32i32s.f32.v8i32.v4i32(i32 %var, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 1, i32 %var)397 %val3 = call {<4 x float>, i32} @llvm.amdgcn.image.sample.1d.v4f32i32.f32.v8i32.v4i32(i32 %var, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 1, i32 %var)398 ret void399}400 401declare <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16.v8i32(i32, i16, <8 x i32>, i32, i32)402define amdgpu_ps void @load_1d_a16(<8 x i32> inreg %rsrc, <2 x i16> %coords, i16 %s, i32 %var) {403 ; CHECK: immarg operand has non-immediate parameter404 ; CHECK-NEXT: i32 %var405 ; CHECK-NEXT: %val0 = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16.v8i32(i32 %var, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)406 %val0 = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16.v8i32(i32 %var, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)407 408 ; CHECK: immarg operand has non-immediate parameter409 ; CHECK-NEXT: i32 %var410 ; CHECK-NEXT: %val1 = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16.v8i32(i32 15, i16 %s, <8 x i32> %rsrc, i32 %var, i32 0)411 %val1 = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16.v8i32(i32 15, i16 %s, <8 x i32> %rsrc, i32 %var, i32 0)412 413 ; CHECK: immarg operand has non-immediate parameter414 ; CHECK-NEXT: i32 %var415 ; CHECK-NEXT: %val2 = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16.v8i32(i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 %var)416 %val2 = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16.v8i32(i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 %var)417 ret void418}419 420declare i32 @llvm.amdgcn.raw.buffer.atomic.swap.i32(i32, <4 x i32>, i32, i32, i32)421define amdgpu_ps void @raw_buffer_atomic_swap(<4 x i32> inreg %rsrc, i32 %data, i32 %var) {422 ; CHECK: immarg operand has non-immediate parameter423 ; CHECK-NEXT: i32 %var424 ; CHECK-NEXT: %val2 = call i32 @llvm.amdgcn.raw.buffer.atomic.swap.i32(i32 %data, <4 x i32> %rsrc, i32 0, i32 0, i32 %var)425 %val2 = call i32 @llvm.amdgcn.raw.buffer.atomic.swap.i32(i32 %data, <4 x i32> %rsrc, i32 0, i32 0, i32 %var)426 ret void427}428 429declare i32 @llvm.amdgcn.image.atomic.swap.1d.i32.i32.v8i32(i32, i32, <8 x i32>, i32, i32)430define amdgpu_ps void @atomic_swap_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s, i32 %val) {431 ; CHECK: immarg operand has non-immediate parameter432 ; CHECK-NEXT: i32 %val433 ; CHECK-NEXT: %val0 = call i32 @llvm.amdgcn.image.atomic.swap.1d.i32.i32.v8i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 %val, i32 0)434 %val0 = call i32 @llvm.amdgcn.image.atomic.swap.1d.i32.i32.v8i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 %val, i32 0)435 436 ; CHECK: immarg operand has non-immediate parameter437 ; CHECK-NEXT: i32 %val438 ; CHECK-NEXT: %val1 = call i32 @llvm.amdgcn.image.atomic.swap.1d.i32.i32.v8i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 %val)439 %val1 = call i32 @llvm.amdgcn.image.atomic.swap.1d.i32.i32.v8i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 %val)440 ret void441}442 443declare i32 @llvm.amdgcn.image.atomic.cmpswap.1d.i32.i32.v8i32(i32, i32, i32, <8 x i32>, i32, i32) #0444define amdgpu_ps void @atomic_cmpswap_1d(<8 x i32> inreg %rsrc, i32 %cmp, i32 %swap, i32 %s, i32 %val) {445 ; CHECK: immarg operand has non-immediate parameter446 ; CHECK-NEXT: i32 %val447 ; CHECK-NEXT: %val0 = call i32 @llvm.amdgcn.image.atomic.cmpswap.1d.i32.i32.v8i32(i32 %cmp, i32 %swap, i32 %s, <8 x i32> %rsrc, i32 %val, i32 0)448 %val0 = call i32 @llvm.amdgcn.image.atomic.cmpswap.1d.i32.i32.v8i32(i32 %cmp, i32 %swap, i32 %s, <8 x i32> %rsrc, i32 %val, i32 0)449 450 ; CHECK: immarg operand has non-immediate parameter451 ; CHECK-NEXT: i32 %val452 ; CHECK-NEXT: %val1 = call i32 @llvm.amdgcn.image.atomic.cmpswap.1d.i32.i32.v8i32(i32 %cmp, i32 %swap, i32 %s, <8 x i32> %rsrc, i32 0, i32 %val)453 %val1 = call i32 @llvm.amdgcn.image.atomic.cmpswap.1d.i32.i32.v8i32(i32 %cmp, i32 %swap, i32 %s, <8 x i32> %rsrc, i32 0, i32 %val)454 ret void455}456 457declare float @llvm.amdgcn.fdot2(<2 x half>, <2 x half>, float, i1)458define float @test_fdot2(<2 x half> %arg0, <2 x half> %arg1, float %arg2, i1 %arg3) {459 ; CHECK: immarg operand has non-immediate parameter460 ; CHECK-NEXT: i1 %arg3461 ; CHECK-NEXT: %val = call float @llvm.amdgcn.fdot2(<2 x half> %arg0, <2 x half> %arg1, float %arg2, i1 %arg3)462 %val = call float @llvm.amdgcn.fdot2(<2 x half> %arg0, <2 x half> %arg1, float %arg2, i1 %arg3)463 ret float %val464}465 466declare i32 @llvm.amdgcn.sdot2(<2 x i16>, <2 x i16>, i32, i1)467define i32 @test_sdot2(<2 x i16> %arg0, <2 x i16> %arg1, i32 %arg2, i1 %arg3) {468 ; CHECK: immarg operand has non-immediate parameter469 ; CHECK-NEXT: i1 %arg3470 ; CHECK-NEXT: %val = call i32 @llvm.amdgcn.sdot2(<2 x i16> %arg0, <2 x i16> %arg1, i32 %arg2, i1 %arg3)471 %val = call i32 @llvm.amdgcn.sdot2(<2 x i16> %arg0, <2 x i16> %arg1, i32 %arg2, i1 %arg3)472 ret i32 %val473}474 475declare i32 @llvm.amdgcn.udot2(<2 x i16>, <2 x i16>, i32, i1)476define i32 @test_udot2(<2 x i16> %arg0, <2 x i16> %arg1, i32 %arg2, i1 %arg3) {477 ; CHECK: immarg operand has non-immediate parameter478 ; CHECK-NEXT: i1 %arg3479 ; CHECK-NEXT: %val = call i32 @llvm.amdgcn.udot2(<2 x i16> %arg0, <2 x i16> %arg1, i32 %arg2, i1 %arg3)480 %val = call i32 @llvm.amdgcn.udot2(<2 x i16> %arg0, <2 x i16> %arg1, i32 %arg2, i1 %arg3)481 ret i32 %val482}483 484declare i32 @llvm.amdgcn.sdot4(i32, i32, i32, i1)485define i32 @test_sdot4(i32 %arg0, i32 %arg1, i32 %arg2, i1 %arg3) {486 ; CHECK: immarg operand has non-immediate parameter487 ; CHECK-NEXT: i1 %arg3488 ; CHECK-NEXT: %val = call i32 @llvm.amdgcn.sdot4(i32 %arg0, i32 %arg1, i32 %arg2, i1 %arg3)489 %val = call i32 @llvm.amdgcn.sdot4(i32 %arg0, i32 %arg1, i32 %arg2, i1 %arg3)490 ret i32 %val491}492 493declare i32 @llvm.amdgcn.udot4(i32, i32, i32, i1)494define i32 @test_udot4(i32 %arg0, i32 %arg1, i32 %arg2, i1 %arg3) {495 ; CHECK: immarg operand has non-immediate parameter496 ; CHECK-NEXT: i1 %arg3497 ; CHECK-NEXT: %val = call i32 @llvm.amdgcn.udot4(i32 %arg0, i32 %arg1, i32 %arg2, i1 %arg3)498 %val = call i32 @llvm.amdgcn.udot4(i32 %arg0, i32 %arg1, i32 %arg2, i1 %arg3)499 ret i32 %val500}501 502declare i32 @llvm.amdgcn.permlane16.i32(i32, i32, i32, i32, i1, i1)503define i32 @test_permlane16(ptr addrspace(1) %out, i32 %arg0, i32 %arg1, i32 %arg2, i1 %arg3, i1 %arg4) {504 ; CHECK: immarg operand has non-immediate parameter505 ; CHECK-NEXT: i1 %arg3506 ; CHECK-NEXT: %v1 = call i32 @llvm.amdgcn.permlane16.i32(i32 %arg0, i32 %arg0, i32 %arg1, i32 %arg2, i1 %arg3, i1 false)507 %v1 = call i32 @llvm.amdgcn.permlane16.i32(i32 %arg0, i32 %arg0, i32 %arg1, i32 %arg2, i1 %arg3, i1 false)508 509 ; CHECK: immarg operand has non-immediate parameter510 ; CHECK-NEXT: i1 %arg4511 ; CHECK-NEXT: call i32 @llvm.amdgcn.permlane16.i32(i32 %v2, i32 %arg0, i32 %arg1, i32 %arg2, i1 false, i1 %arg4)512 %v2 = call i32 @llvm.amdgcn.permlane16.i32(i32 %v2, i32 %arg0, i32 %arg1, i32 %arg2, i1 false, i1 %arg4)513 ret i32 %v2514}515 516declare i32 @llvm.amdgcn.permlanex16.i32(i32, i32, i32, i32, i1, i1)517define i32 @test_permlanex16(ptr addrspace(1) %out, i32 %arg0, i32 %arg1, i32 %arg2, i1 %arg3, i1 %arg4) {518 ; CHECK: immarg operand has non-immediate parameter519 ; CHECK-NEXT: i1 %arg3520 ; CHECK-NEXT: %v1 = call i32 @llvm.amdgcn.permlanex16.i32(i32 %arg0, i32 %arg0, i32 %arg1, i32 %arg2, i1 %arg3, i1 false)521 %v1 = call i32 @llvm.amdgcn.permlanex16.i32(i32 %arg0, i32 %arg0, i32 %arg1, i32 %arg2, i1 %arg3, i1 false)522 523 ; CHECK: immarg operand has non-immediate parameter524 ; CHECK-NEXT: i1 %arg4525 ; CHECK-NEXT: call i32 @llvm.amdgcn.permlanex16.i32(i32 %v2, i32 %arg0, i32 %arg1, i32 %arg2, i1 false, i1 %arg4)526 %v2 = call i32 @llvm.amdgcn.permlanex16.i32(i32 %v2, i32 %arg0, i32 %arg1, i32 %arg2, i1 false, i1 %arg4)527 ret i32 %v2528}529 530declare float @llvm.amdgcn.interp.p1(float, i32, i32, i32)531define void @test_interp_p1(float %arg0, i32 %arg1, i32 %arg2, i32 %arg3) {532 ; CHECK: immarg operand has non-immediate parameter533 ; CHECK-NEXT: i32 %arg1534 ; CHECK-NEXT: %val0 = call float @llvm.amdgcn.interp.p1(float %arg0, i32 %arg1, i32 0, i32 0)535 %val0 = call float @llvm.amdgcn.interp.p1(float %arg0, i32 %arg1, i32 0, i32 0)536 store volatile float %val0, ptr addrspace(1) undef537 538 ; CHECK: immarg operand has non-immediate parameter539 ; CHECK-NEXT: i32 %arg2540 ; CHECK-NEXT: %val1 = call float @llvm.amdgcn.interp.p1(float %arg0, i32 0, i32 %arg2, i32 0)541 %val1 = call float @llvm.amdgcn.interp.p1(float %arg0, i32 0, i32 %arg2, i32 0)542 store volatile float %val1, ptr addrspace(1) undef543 ret void544}545 546declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32)547define void @test_interp_p2(float %arg0, float %arg1, i32 %arg2, i32 %arg3, i32 %arg4) {548 ; CHECK: immarg operand has non-immediate parameter549 ; CHECK-NEXT: i32 %arg2550 ; CHECK-NEXT: %val0 = call float @llvm.amdgcn.interp.p2(float %arg0, float %arg1, i32 %arg2, i32 0, i32 0)551 552 %val0 = call float @llvm.amdgcn.interp.p2(float %arg0, float %arg1, i32 %arg2, i32 0, i32 0)553 store volatile float %val0, ptr addrspace(1) undef554 555 ; CHECK: immarg operand has non-immediate parameter556 ; CHECK-NEXT: i32 %arg3557 ; CHECK-NEXT: %val1 = call float @llvm.amdgcn.interp.p2(float %arg0, float %arg1, i32 0, i32 %arg3, i32 0)558 %val1 = call float @llvm.amdgcn.interp.p2(float %arg0, float %arg1, i32 0, i32 %arg3, i32 0)559 store volatile float %val1, ptr addrspace(1) undef560 ret void561}562 563declare float @llvm.amdgcn.interp.mov(i32, i32, i32, i32)564define void @test_interp_mov(i32 %arg0, i32 %arg1, i32 %arg2, i32 %arg3) {565 ; CHECK: immarg operand has non-immediate parameter566 ; CHECK-NEXT: i32 %arg0567 ; CHECK-NEXT: %val0 = call float @llvm.amdgcn.interp.mov(i32 %arg0, i32 0, i32 0, i32 0)568 %val0 = call float @llvm.amdgcn.interp.mov(i32 %arg0, i32 0, i32 0, i32 0)569 store volatile float %val0, ptr addrspace(1) undef570 571 ; CHECK: immarg operand has non-immediate parameter572 ; CHECK-NEXT: i32 %arg1573 ; CHECK-NEXT: %val1 = call float @llvm.amdgcn.interp.mov(i32 0, i32 %arg1, i32 0, i32 0)574 %val1 = call float @llvm.amdgcn.interp.mov(i32 0, i32 %arg1, i32 0, i32 0)575 store volatile float %val1, ptr addrspace(1) undef576 577 ; CHECK: immarg operand has non-immediate parameter578 ; CHECK-NEXT: i32 %arg2579 ; CHECK-NEXT: %val2 = call float @llvm.amdgcn.interp.mov(i32 0, i32 0, i32 %arg2, i32 0)580 %val2 = call float @llvm.amdgcn.interp.mov(i32 0, i32 0, i32 %arg2, i32 0)581 store volatile float %val2, ptr addrspace(1) undef582 583 ret void584}585 586declare float @llvm.amdgcn.interp.p1.f16(float, i32, i32, i1, i32)587define void @test_interp_p1_f16(float %arg0, i32 %arg1, i32 %arg2, i1 %arg3, i32 %arg4) {588 ; CHECK: immarg operand has non-immediate parameter589 ; CHECK-NEXT: i32 %arg1590 ; CHECK-NEXT:%val0 = call float @llvm.amdgcn.interp.p1.f16(float %arg0, i32 %arg1, i32 2, i1 false, i32 %arg4)591 %val0 = call float @llvm.amdgcn.interp.p1.f16(float %arg0, i32 %arg1, i32 2, i1 0, i32 %arg4)592 store volatile float %val0, ptr addrspace(1) undef593 594 ; CHECK: immarg operand has non-immediate parameter595 ; CHECK-NEXT:i32 %arg2596 ; CHECK-NEXT: %val1 = call float @llvm.amdgcn.interp.p1.f16(float %arg0, i32 0, i32 %arg2, i1 false, i32 %arg4)597 %val1 = call float @llvm.amdgcn.interp.p1.f16(float %arg0, i32 0, i32 %arg2, i1 0, i32 %arg4)598 store volatile float %val1, ptr addrspace(1) undef599 600 ; CHECK: immarg operand has non-immediate parameter601 ; CHECK-NEXT:i1 %arg3602 ; CHECK-NEXT: %val2 = call float @llvm.amdgcn.interp.p1.f16(float %arg0, i32 0, i32 0, i1 %arg3, i32 %arg4)603 %val2 = call float @llvm.amdgcn.interp.p1.f16(float %arg0, i32 0, i32 0, i1 %arg3, i32 %arg4)604 store volatile float %val2, ptr addrspace(1) undef605 606 ret void607}608 609declare half @llvm.amdgcn.interp.p2.f16(float, float, i32, i32, i1, i32)610define void @test_interp_p2_f16(float %arg0, float %arg1, i32 %arg2, i32 %arg3, i1 %arg4, i32 %arg5) {611 ; CHECK: immarg operand has non-immediate parameter612 ; CHECK-NEXT: i32 %arg2613 ; CHECK-NEXT: %val0 = call half @llvm.amdgcn.interp.p2.f16(float %arg0, float %arg1, i32 %arg2, i32 2, i1 false, i32 %arg5)614 %val0 = call half @llvm.amdgcn.interp.p2.f16(float %arg0, float %arg1, i32 %arg2, i32 2, i1 false, i32 %arg5)615 store volatile half %val0, ptr addrspace(1) undef616 617 ; CHECK: immarg operand has non-immediate parameter618 ; CHECK-NEXT: i32 %arg3619 ; CHECK-NEXT: %val1 = call half @llvm.amdgcn.interp.p2.f16(float %arg0, float %arg1, i32 0, i32 %arg3, i1 false, i32 %arg5)620 %val1 = call half @llvm.amdgcn.interp.p2.f16(float %arg0, float %arg1, i32 0, i32 %arg3, i1 false, i32 %arg5)621 store volatile half %val1, ptr addrspace(1) undef622 623 ; CHECK: immarg operand has non-immediate parameter624 ; CHECK-NEXT: i1 %arg4625 ; CHECK-NEXT: %val2 = call half @llvm.amdgcn.interp.p2.f16(float %arg0, float %arg1, i32 0, i32 0, i1 %arg4, i32 %arg5)626 %val2 = call half @llvm.amdgcn.interp.p2.f16(float %arg0, float %arg1, i32 0, i32 0, i1 %arg4, i32 %arg5)627 store volatile half %val2, ptr addrspace(1) undef628 629 ret void630}631 632declare <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float, float, <32 x float>, i32, i32, i32)633define void @test_mfma_f32_32x32x1f32(float %arg0, float %arg1, <32 x float> %arg2, i32 %arg3, i32 %arg4, i32 %arg5) {634 ; CHECK: immarg operand has non-immediate parameter635 ; CHECK-NEXT: i32 %arg3636 ; CHECK-NEXT: %val0 = call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float %arg0, float %arg1, <32 x float> %arg2, i32 %arg3, i32 2, i32 3)637 %val0 = call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float %arg0, float %arg1, <32 x float> %arg2, i32 %arg3, i32 2, i32 3)638 store volatile <32 x float> %val0, ptr addrspace(1) undef639 640 ; CHECK: immarg operand has non-immediate parameter641 ; CHECK-NEXT: i32 %arg4642 ; CHECK-NEXT: %val1 = call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float %arg0, float %arg1, <32 x float> %arg2, i32 1, i32 %arg4, i32 3)643 %val1 = call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float %arg0, float %arg1, <32 x float> %arg2, i32 1, i32 %arg4, i32 3)644 store volatile <32 x float> %val1, ptr addrspace(1) undef645 646 ; CHECK: immarg operand has non-immediate parameter647 ; CHECK-NEXT: i32 %arg5648 ; CHECK-NEXT: %val2 = call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float %arg0, float %arg1, <32 x float> %arg2, i32 1, i32 2, i32 %arg5)649 %val2 = call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float %arg0, float %arg1, <32 x float> %arg2, i32 1, i32 2, i32 %arg5)650 store volatile <32 x float> %val2, ptr addrspace(1) undef651 652 ret void653}654