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1# RUN: llvm-exegesis -mtriple=riscv64 -mcpu=sifive-x280 -benchmark-phase=assemble-measured-code --mode=latency --opcode-name=PseudoVMUL_VV_MF4_MASK \2# RUN: --max-configs-per-opcode=1000 --min-instructions=100 | FileCheck %s --check-prefix=FRAC-LMUL3# RUN: llvm-exegesis -mtriple=riscv64 -mcpu=sifive-x280 -benchmark-phase=assemble-measured-code --mode=latency \4# RUN: --opcode-name=PseudoVFADD_VFPR16_M1_E16,PseudoVFADD_VV_M2_E16,PseudoVFCLASS_V_MF2 --max-configs-per-opcode=1000 --min-instructions=100 | \5# RUN: FileCheck %s --check-prefix=FP6# RUN: llvm-exegesis -mtriple=riscv64 -mcpu=sifive-x280 -benchmark-phase=assemble-measured-code --mode=inverse_throughput \7# RUN: --opcode-name=PseudoVSEXT_VF8_M2,PseudoVZEXT_VF8_M2 --max-configs-per-opcode=1000 --min-instructions=100 | \8# RUN: FileCheck %s --check-prefix=VEXT9# RUN: llvm-exegesis -mtriple=riscv64 -mcpu=sifive-p470 -benchmark-phase=assemble-measured-code --mode=latency \10# RUN: --opcode-name=PseudoVFREDUSUM_VS_M1_E16 --max-configs-per-opcode=1000 --min-instructions=100 | \11# RUN: FileCheck %s --check-prefix=VFRED --allow-empty12# UNSUPPORTED: expensive_checks13 14# Make sure only the supported SEWs are generated for fractional LMUL.15# FRAC-LMUL: PseudoVMUL_VV_MF4_MASK16# FRAC-LMUL: SEW: e817# FRAC-LMUL: SEW: e1618# FRAC-LMUL-NOT: SEW: e{{(32|64)}}19 20# Make sure only SEWs that are equal to the supported FLEN are generated21# FP: PseudoVFADD_VFPR16_M1_E1622# FP-NOT: SEW: e823# FP: PseudoVFADD_VV_M2_E1624# FP-NOT: SEW: e825# FP: PseudoVFCLASS_V_MF226# FP-NOT: SEW: e827 28# VS/ZEXT can only operate on SEW that will not lead to invalid EEW on the29# source operand.30# VEXT: PseudoVSEXT_VF8_M231# VEXT-NOT: SEW: e832# VEXT-NOT: SEW: e1633# VEXT-NOT: SEW: e3234# VEXT: SEW: e6435# VEXT: PseudoVZEXT_VF8_M236# VEXT-NOT: SEW: e837# VEXT-NOT: SEW: e1638# VEXT-NOT: SEW: e3239# VEXT: SEW: e6440 41# P470 doesn't have Zvfh so 16-bit vfredusum shouldn't exist42# VFRED-NOT: PseudoVFREDUSUM_VS_M1_E1643