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1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py2# RUN: llvm-mca -mtriple=aarch64 -mcpu=cortex-a55 --all-stats --iterations=2 < %s | FileCheck %s3 4ldr w4, [x2], #45ldr w5, [x3]6madd w0, w5, w4, w07add x3, x3, x138subs x1, x1, #19str w0, [x21, x18, lsl #2]10 11# CHECK: Iterations: 212# CHECK-NEXT: Instructions: 1213# CHECK-NEXT: Total Cycles: 1714# CHECK-NEXT: Total uOps: 1415 16# CHECK: Dispatch Width: 217# CHECK-NEXT: uOps Per Cycle: 0.8218# CHECK-NEXT: IPC: 0.7119# CHECK-NEXT: Block RThroughput: 3.520 21# CHECK: Instruction Info:22# CHECK-NEXT: [1]: #uOps23# CHECK-NEXT: [2]: Latency24# CHECK-NEXT: [3]: RThroughput25# CHECK-NEXT: [4]: MayLoad26# CHECK-NEXT: [5]: MayStore27# CHECK-NEXT: [6]: HasSideEffects (U)28 29# CHECK: [1] [2] [3] [4] [5] [6] Instructions:30# CHECK-NEXT: 2 3 1.00 * ldr w4, [x2], #431# CHECK-NEXT: 1 3 1.00 * ldr w5, [x3]32# CHECK-NEXT: 1 4 1.00 madd w0, w5, w4, w033# CHECK-NEXT: 1 3 0.50 add x3, x3, x1334# CHECK-NEXT: 1 3 0.50 subs x1, x1, #135# CHECK-NEXT: 1 1 1.00 * str w0, [x21, x18, lsl #2]36 37# CHECK: Dynamic Dispatch Stall Cycles:38# CHECK-NEXT: RAT - Register unavailable: 8 (47.1%)39# CHECK-NEXT: RCU - Retire tokens unavailable: 040# CHECK-NEXT: SCHEDQ - Scheduler full: 041# CHECK-NEXT: LQ - Load queue full: 042# CHECK-NEXT: SQ - Store queue full: 043# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 044# CHECK-NEXT: USH - Uncategorised Structural Hazard: 045 46# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:47# CHECK-NEXT: [# dispatched], [# cycles]48# CHECK-NEXT: 0, 7 (41.2%)49# CHECK-NEXT: 1, 6 (35.3%)50# CHECK-NEXT: 2, 4 (23.5%)51 52# CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:53# CHECK-NEXT: [# issued], [# cycles]54# CHECK-NEXT: 0, 7 (41.2%)55# CHECK-NEXT: 1, 6 (35.3%)56# CHECK-NEXT: 2, 4 (23.5%)57 58# CHECK: Scheduler's queue usage:59# CHECK-NEXT: No scheduler resources used.60 61# CHECK: Register File statistics:62# CHECK-NEXT: Total number of mappings created: 1463# CHECK-NEXT: Max number of mappings used: 464 65# CHECK: Resources:66# CHECK-NEXT: [0.0] - CortexA55UnitALU67# CHECK-NEXT: [0.1] - CortexA55UnitALU68# CHECK-NEXT: [1] - CortexA55UnitB69# CHECK-NEXT: [2] - CortexA55UnitDiv70# CHECK-NEXT: [3.0] - CortexA55UnitFPALU71# CHECK-NEXT: [3.1] - CortexA55UnitFPALU72# CHECK-NEXT: [4] - CortexA55UnitFPDIV73# CHECK-NEXT: [5.0] - CortexA55UnitFPMAC74# CHECK-NEXT: [5.1] - CortexA55UnitFPMAC75# CHECK-NEXT: [6] - CortexA55UnitLd76# CHECK-NEXT: [7] - CortexA55UnitMAC77# CHECK-NEXT: [8] - CortexA55UnitSt78 79# CHECK: Resource pressure per iteration:80# CHECK-NEXT: [0.0] [0.1] [1] [2] [3.0] [3.1] [4] [5.0] [5.1] [6] [7] [8]81# CHECK-NEXT: 1.00 1.00 - - - - - - - 2.00 1.00 1.0082 83# CHECK: Resource pressure by instruction:84# CHECK-NEXT: [0.0] [0.1] [1] [2] [3.0] [3.1] [4] [5.0] [5.1] [6] [7] [8] Instructions:85# CHECK-NEXT: - - - - - - - - - 1.00 - - ldr w4, [x2], #486# CHECK-NEXT: - - - - - - - - - 1.00 - - ldr w5, [x3]87# CHECK-NEXT: - - - - - - - - - - 1.00 - madd w0, w5, w4, w088# CHECK-NEXT: - 1.00 - - - - - - - - - - add x3, x3, x1389# CHECK-NEXT: 1.00 - - - - - - - - - - - subs x1, x1, #190# CHECK-NEXT: - - - - - - - - - - - 1.00 str w0, [x21, x18, lsl #2]91