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1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py2# RUN: llvm-mca -mtriple=aarch64-linux-gnu -mcpu=exynos-m3 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M33# RUN: llvm-mca -mtriple=aarch64-linux-gnu -mcpu=exynos-m4 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M44# RUN: llvm-mca -mtriple=aarch64-linux-gnu -mcpu=exynos-m5 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M55 6ld1 {v0.s}[0], [sp]7ld1r {v0.2s}, [sp]8ld1 {v0.2s}, [sp]9ld1 {v0.2s, v1.2s}, [sp]10ld1 {v0.2s, v1.2s, v2.2s}, [sp]11ld1 {v0.2s, v1.2s, v2.2s, v3.2s}, [sp]12 13ld1 {v0.d}[0], [sp]14ld1r {v0.2d}, [sp]15ld1 {v0.2d}, [sp]16ld1 {v0.2d, v1.2d}, [sp]17ld1 {v0.2d, v1.2d, v2.2d}, [sp]18ld1 {v0.2d, v1.2d, v2.2d, v3.2d}, [sp]19 20ld1 {v0.s}[0], [sp], #421ld1r {v0.2s}, [sp], #422ld1 {v0.2s}, [sp], #823ld1 {v0.2s, v1.2s}, [sp], #1624ld1 {v0.2s, v1.2s, v2.2s}, [sp], #2425ld1 {v0.2s, v1.2s, v2.2s, v3.2s}, [sp], #3226 27ld1 {v0.d}[0], [sp], #828ld1r {v0.2d}, [sp], #829ld1 {v0.2d}, [sp], #1630ld1 {v0.2d, v1.2d}, [sp], #3231ld1 {v0.2d, v1.2d, v2.2d}, [sp], #4832ld1 {v0.2d, v1.2d, v2.2d, v3.2d}, [sp], #6433 34ld1 {v0.s}[0], [sp], x035ld1r {v0.2s}, [sp], x036ld1 {v0.2s}, [sp], x037ld1 {v0.2s, v1.2s}, [sp], x038ld1 {v0.2s, v1.2s, v2.2s}, [sp], x039ld1 {v0.2s, v1.2s, v2.2s, v3.2s}, [sp], x040 41ld1 {v0.d}[0], [sp], x042ld1r {v0.2d}, [sp], x043ld1 {v0.2d}, [sp], x044ld1 {v0.2d, v1.2d}, [sp], x045ld1 {v0.2d, v1.2d, v2.2d}, [sp], x046ld1 {v0.2d, v1.2d, v2.2d, v3.2d}, [sp], x047 48# ALL: Iterations: 10049# ALL-NEXT: Instructions: 360050 51# M3-NEXT: Total Cycles: 1490352# M4-NEXT: Total Cycles: 1470353# M5-NEXT: Total Cycles: 1720354 55# ALL-NEXT: Total uOps: 1020056 57# ALL: Dispatch Width: 658 59# M3-NEXT: uOps Per Cycle: 0.6860# M3-NEXT: IPC: 0.2461 62# M4-NEXT: uOps Per Cycle: 0.6963# M4-NEXT: IPC: 0.2464 65# M5-NEXT: uOps Per Cycle: 0.5966# M5-NEXT: IPC: 0.2167 68# ALL-NEXT: Block RThroughput: 39.069 70# ALL: Instruction Info:71# ALL-NEXT: [1]: #uOps72# ALL-NEXT: [2]: Latency73# ALL-NEXT: [3]: RThroughput74# ALL-NEXT: [4]: MayLoad75# ALL-NEXT: [5]: MayStore76# ALL-NEXT: [6]: HasSideEffects (U)77 78# ALL: [1] [2] [3] [4] [5] [6] Instructions:79 80# M3-NEXT: 2 7 1.00 * ld1 { v0.s }[0], [sp]81# M3-NEXT: 1 5 0.50 * ld1r { v0.2s }, [sp]82# M3-NEXT: 1 5 0.50 * ld1 { v0.2s }, [sp]83# M3-NEXT: 2 5 1.00 * ld1 { v0.2s, v1.2s }, [sp]84# M3-NEXT: 3 6 1.50 * ld1 { v0.2s, v1.2s, v2.2s }, [sp]85# M3-NEXT: 4 6 2.00 * ld1 { v0.2s, v1.2s, v2.2s, v3.2s }, [sp]86# M3-NEXT: 2 6 1.00 * ld1 { v0.d }[0], [sp]87# M3-NEXT: 1 5 0.50 * ld1r { v0.2d }, [sp]88# M3-NEXT: 1 5 0.50 * ld1 { v0.2d }, [sp]89# M3-NEXT: 2 5 1.00 * ld1 { v0.2d, v1.2d }, [sp]90# M3-NEXT: 3 6 1.50 * ld1 { v0.2d, v1.2d, v2.2d }, [sp]91# M3-NEXT: 4 6 2.00 * ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [sp]92# M3-NEXT: 3 7 1.00 * ld1 { v0.s }[0], [sp], #493# M3-NEXT: 2 5 0.50 * ld1r { v0.2s }, [sp], #494# M3-NEXT: 2 5 0.50 * ld1 { v0.2s }, [sp], #895# M3-NEXT: 3 5 1.00 * ld1 { v0.2s, v1.2s }, [sp], #1696# M3-NEXT: 4 6 1.50 * ld1 { v0.2s, v1.2s, v2.2s }, [sp], #2497# M3-NEXT: 5 6 2.00 * ld1 { v0.2s, v1.2s, v2.2s, v3.2s }, [sp], #3298# M3-NEXT: 3 6 1.00 * ld1 { v0.d }[0], [sp], #899# M3-NEXT: 2 5 0.50 * ld1r { v0.2d }, [sp], #8100# M3-NEXT: 2 5 0.50 * ld1 { v0.2d }, [sp], #16101# M3-NEXT: 3 5 1.00 * ld1 { v0.2d, v1.2d }, [sp], #32102# M3-NEXT: 4 6 1.50 * ld1 { v0.2d, v1.2d, v2.2d }, [sp], #48103# M3-NEXT: 5 6 2.00 * ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [sp], #64104# M3-NEXT: 3 7 1.00 * ld1 { v0.s }[0], [sp], x0105# M3-NEXT: 2 5 0.50 * ld1r { v0.2s }, [sp], x0106# M3-NEXT: 2 5 0.50 * ld1 { v0.2s }, [sp], x0107# M3-NEXT: 3 5 1.00 * ld1 { v0.2s, v1.2s }, [sp], x0108# M3-NEXT: 4 6 1.50 * ld1 { v0.2s, v1.2s, v2.2s }, [sp], x0109# M3-NEXT: 5 6 2.00 * ld1 { v0.2s, v1.2s, v2.2s, v3.2s }, [sp], x0110# M3-NEXT: 3 6 1.00 * ld1 { v0.d }[0], [sp], x0111# M3-NEXT: 2 5 0.50 * ld1r { v0.2d }, [sp], x0112# M3-NEXT: 2 5 0.50 * ld1 { v0.2d }, [sp], x0113# M3-NEXT: 3 5 1.00 * ld1 { v0.2d, v1.2d }, [sp], x0114# M3-NEXT: 4 6 1.50 * ld1 { v0.2d, v1.2d, v2.2d }, [sp], x0115# M3-NEXT: 5 6 2.00 * ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [sp], x0116 117# M4-NEXT: 2 6 1.00 * ld1 { v0.s }[0], [sp]118# M4-NEXT: 1 5 0.50 * ld1r { v0.2s }, [sp]119# M4-NEXT: 1 5 0.50 * ld1 { v0.2s }, [sp]120# M4-NEXT: 2 5 1.00 * ld1 { v0.2s, v1.2s }, [sp]121# M4-NEXT: 3 6 1.50 * ld1 { v0.2s, v1.2s, v2.2s }, [sp]122# M4-NEXT: 4 6 2.00 * ld1 { v0.2s, v1.2s, v2.2s, v3.2s }, [sp]123# M4-NEXT: 2 6 1.00 * ld1 { v0.d }[0], [sp]124# M4-NEXT: 1 5 0.50 * ld1r { v0.2d }, [sp]125# M4-NEXT: 1 5 0.50 * ld1 { v0.2d }, [sp]126# M4-NEXT: 2 5 1.00 * ld1 { v0.2d, v1.2d }, [sp]127# M4-NEXT: 3 6 1.50 * ld1 { v0.2d, v1.2d, v2.2d }, [sp]128# M4-NEXT: 4 6 2.00 * ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [sp]129# M4-NEXT: 3 6 1.00 * ld1 { v0.s }[0], [sp], #4130# M4-NEXT: 2 5 0.50 * ld1r { v0.2s }, [sp], #4131# M4-NEXT: 2 5 0.50 * ld1 { v0.2s }, [sp], #8132# M4-NEXT: 3 5 1.00 * ld1 { v0.2s, v1.2s }, [sp], #16133# M4-NEXT: 4 6 1.50 * ld1 { v0.2s, v1.2s, v2.2s }, [sp], #24134# M4-NEXT: 5 6 2.00 * ld1 { v0.2s, v1.2s, v2.2s, v3.2s }, [sp], #32135# M4-NEXT: 3 6 1.00 * ld1 { v0.d }[0], [sp], #8136# M4-NEXT: 2 5 0.50 * ld1r { v0.2d }, [sp], #8137# M4-NEXT: 2 5 0.50 * ld1 { v0.2d }, [sp], #16138# M4-NEXT: 3 5 1.00 * ld1 { v0.2d, v1.2d }, [sp], #32139# M4-NEXT: 4 6 1.50 * ld1 { v0.2d, v1.2d, v2.2d }, [sp], #48140# M4-NEXT: 5 6 2.00 * ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [sp], #64141# M4-NEXT: 3 6 1.00 * ld1 { v0.s }[0], [sp], x0142# M4-NEXT: 2 5 0.50 * ld1r { v0.2s }, [sp], x0143# M4-NEXT: 2 5 0.50 * ld1 { v0.2s }, [sp], x0144# M4-NEXT: 3 5 1.00 * ld1 { v0.2s, v1.2s }, [sp], x0145# M4-NEXT: 4 6 1.50 * ld1 { v0.2s, v1.2s, v2.2s }, [sp], x0146# M4-NEXT: 5 6 2.00 * ld1 { v0.2s, v1.2s, v2.2s, v3.2s }, [sp], x0147# M4-NEXT: 3 6 1.00 * ld1 { v0.d }[0], [sp], x0148# M4-NEXT: 2 5 0.50 * ld1r { v0.2d }, [sp], x0149# M4-NEXT: 2 5 0.50 * ld1 { v0.2d }, [sp], x0150# M4-NEXT: 3 5 1.00 * ld1 { v0.2d, v1.2d }, [sp], x0151# M4-NEXT: 4 6 1.50 * ld1 { v0.2d, v1.2d, v2.2d }, [sp], x0152# M4-NEXT: 5 6 2.00 * ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [sp], x0153 154# M5-NEXT: 2 7 1.00 * ld1 { v0.s }[0], [sp]155# M5-NEXT: 1 6 0.50 * ld1r { v0.2s }, [sp]156# M5-NEXT: 1 6 0.50 * ld1 { v0.2s }, [sp]157# M5-NEXT: 2 6 1.00 * ld1 { v0.2s, v1.2s }, [sp]158# M5-NEXT: 3 7 1.50 * ld1 { v0.2s, v1.2s, v2.2s }, [sp]159# M5-NEXT: 4 7 2.00 * ld1 { v0.2s, v1.2s, v2.2s, v3.2s }, [sp]160# M5-NEXT: 2 7 1.00 * ld1 { v0.d }[0], [sp]161# M5-NEXT: 1 6 0.50 * ld1r { v0.2d }, [sp]162# M5-NEXT: 1 6 0.50 * ld1 { v0.2d }, [sp]163# M5-NEXT: 2 6 1.00 * ld1 { v0.2d, v1.2d }, [sp]164# M5-NEXT: 3 7 1.50 * ld1 { v0.2d, v1.2d, v2.2d }, [sp]165# M5-NEXT: 4 7 2.00 * ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [sp]166# M5-NEXT: 3 7 1.00 * ld1 { v0.s }[0], [sp], #4167# M5-NEXT: 2 6 0.50 * ld1r { v0.2s }, [sp], #4168# M5-NEXT: 2 6 0.50 * ld1 { v0.2s }, [sp], #8169# M5-NEXT: 3 6 1.00 * ld1 { v0.2s, v1.2s }, [sp], #16170# M5-NEXT: 4 7 1.50 * ld1 { v0.2s, v1.2s, v2.2s }, [sp], #24171# M5-NEXT: 5 7 2.00 * ld1 { v0.2s, v1.2s, v2.2s, v3.2s }, [sp], #32172# M5-NEXT: 3 7 1.00 * ld1 { v0.d }[0], [sp], #8173# M5-NEXT: 2 6 0.50 * ld1r { v0.2d }, [sp], #8174# M5-NEXT: 2 6 0.50 * ld1 { v0.2d }, [sp], #16175# M5-NEXT: 3 6 1.00 * ld1 { v0.2d, v1.2d }, [sp], #32176# M5-NEXT: 4 7 1.50 * ld1 { v0.2d, v1.2d, v2.2d }, [sp], #48177# M5-NEXT: 5 7 2.00 * ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [sp], #64178# M5-NEXT: 3 7 1.00 * ld1 { v0.s }[0], [sp], x0179# M5-NEXT: 2 6 0.50 * ld1r { v0.2s }, [sp], x0180# M5-NEXT: 2 6 0.50 * ld1 { v0.2s }, [sp], x0181# M5-NEXT: 3 6 1.00 * ld1 { v0.2s, v1.2s }, [sp], x0182# M5-NEXT: 4 7 1.50 * ld1 { v0.2s, v1.2s, v2.2s }, [sp], x0183# M5-NEXT: 5 7 2.00 * ld1 { v0.2s, v1.2s, v2.2s, v3.2s }, [sp], x0184# M5-NEXT: 3 7 1.00 * ld1 { v0.d }[0], [sp], x0185# M5-NEXT: 2 6 0.50 * ld1r { v0.2d }, [sp], x0186# M5-NEXT: 2 6 0.50 * ld1 { v0.2d }, [sp], x0187# M5-NEXT: 3 6 1.00 * ld1 { v0.2d, v1.2d }, [sp], x0188# M5-NEXT: 4 7 1.50 * ld1 { v0.2d, v1.2d, v2.2d }, [sp], x0189# M5-NEXT: 5 7 2.00 * ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [sp], x0190