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1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py2# RUN: llvm-mca -mtriple=aarch64-linux-gnu -mcpu=exynos-m3 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M33# RUN: llvm-mca -mtriple=aarch64-linux-gnu -mcpu=exynos-m4 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M44# RUN: llvm-mca -mtriple=aarch64-linux-gnu -mcpu=exynos-m5 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M55 6ld2 {v0.s, v1.s}[0], [sp]7ld2r {v0.2s, v1.2s}, [sp]8ld2 {v0.2s, v1.2s}, [sp]9 10ld2 {v0.d, v1.d}[0], [sp]11ld2r {v0.2d, v1.2d}, [sp]12ld2 {v0.2d, v1.2d}, [sp]13 14ld2 {v0.s, v1.s}[0], [sp], #815ld2r {v0.2s, v1.2s}, [sp], #816ld2 {v0.2s, v1.2s}, [sp], #1617 18ld2 {v0.d, v1.d}[0], [sp], #1619ld2r {v0.2d, v1.2d}, [sp], #1620ld2 {v0.2d, v1.2d}, [sp], #3221 22ld2 {v0.s, v1.s}[0], [sp], x023ld2r {v0.2s, v1.2s}, [sp], x024ld2 {v0.2s, v1.2s}, [sp], x025 26ld2 {v0.d, v1.d}[0], [sp], x027ld2r {v0.2d, v1.2d}, [sp], x028ld2 {v0.2d, v1.2d}, [sp], x029 30# ALL: Iterations: 10031# ALL-NEXT: Instructions: 180032 33# M3-NEXT: Total Cycles: 1000334# M4-NEXT: Total Cycles: 980335# M5-NEXT: Total Cycles: 1110336 37# ALL-NEXT: Total uOps: 540038 39# ALL: Dispatch Width: 640 41# M3-NEXT: uOps Per Cycle: 0.5442# M3-NEXT: IPC: 0.1843# M3-NEXT: Block RThroughput: 42.044 45# M4-NEXT: uOps Per Cycle: 0.5546# M4-NEXT: IPC: 0.1847# M4-NEXT: Block RThroughput: 30.048 49# M5-NEXT: uOps Per Cycle: 0.4950# M5-NEXT: IPC: 0.1651# M5-NEXT: Block RThroughput: 45.052 53# ALL: Instruction Info:54# ALL-NEXT: [1]: #uOps55# ALL-NEXT: [2]: Latency56# ALL-NEXT: [3]: RThroughput57# ALL-NEXT: [4]: MayLoad58# ALL-NEXT: [5]: MayStore59# ALL-NEXT: [6]: HasSideEffects (U)60 61# ALL: [1] [2] [3] [4] [5] [6] Instructions:62 63# M3-NEXT: 3 7 1.00 * ld2 { v0.s, v1.s }[0], [sp]64# M3-NEXT: 2 5 1.00 * ld2r { v0.2s, v1.2s }, [sp]65# M3-NEXT: 2 10 5.00 * ld2 { v0.2s, v1.2s }, [sp]66# M3-NEXT: 3 6 1.00 * ld2 { v0.d, v1.d }[0], [sp]67# M3-NEXT: 2 5 1.00 * ld2r { v0.2d, v1.2d }, [sp]68# M3-NEXT: 2 10 5.00 * ld2 { v0.2d, v1.2d }, [sp]69# M3-NEXT: 4 7 1.00 * ld2 { v0.s, v1.s }[0], [sp], #870# M3-NEXT: 3 5 1.00 * ld2r { v0.2s, v1.2s }, [sp], #871# M3-NEXT: 3 10 5.00 * ld2 { v0.2s, v1.2s }, [sp], #1672# M3-NEXT: 4 6 1.00 * ld2 { v0.d, v1.d }[0], [sp], #1673# M3-NEXT: 3 5 1.00 * ld2r { v0.2d, v1.2d }, [sp], #1674# M3-NEXT: 3 10 5.00 * ld2 { v0.2d, v1.2d }, [sp], #3275# M3-NEXT: 4 7 1.00 * ld2 { v0.s, v1.s }[0], [sp], x076# M3-NEXT: 3 5 1.00 * ld2r { v0.2s, v1.2s }, [sp], x077# M3-NEXT: 3 10 5.00 * ld2 { v0.2s, v1.2s }, [sp], x078# M3-NEXT: 4 6 1.00 * ld2 { v0.d, v1.d }[0], [sp], x079# M3-NEXT: 3 5 1.00 * ld2r { v0.2d, v1.2d }, [sp], x080# M3-NEXT: 3 10 5.00 * ld2 { v0.2d, v1.2d }, [sp], x081 82# M4-NEXT: 3 6 1.00 * ld2 { v0.s, v1.s }[0], [sp]83# M4-NEXT: 2 5 1.00 * ld2r { v0.2s, v1.2s }, [sp]84# M4-NEXT: 2 10 3.00 * ld2 { v0.2s, v1.2s }, [sp]85# M4-NEXT: 3 6 1.00 * ld2 { v0.d, v1.d }[0], [sp]86# M4-NEXT: 2 5 1.00 * ld2r { v0.2d, v1.2d }, [sp]87# M4-NEXT: 2 10 3.00 * ld2 { v0.2d, v1.2d }, [sp]88# M4-NEXT: 4 6 1.00 * ld2 { v0.s, v1.s }[0], [sp], #889# M4-NEXT: 3 5 1.00 * ld2r { v0.2s, v1.2s }, [sp], #890# M4-NEXT: 3 10 3.00 * ld2 { v0.2s, v1.2s }, [sp], #1691# M4-NEXT: 4 6 1.00 * ld2 { v0.d, v1.d }[0], [sp], #1692# M4-NEXT: 3 5 1.00 * ld2r { v0.2d, v1.2d }, [sp], #1693# M4-NEXT: 3 10 3.00 * ld2 { v0.2d, v1.2d }, [sp], #3294# M4-NEXT: 4 6 1.00 * ld2 { v0.s, v1.s }[0], [sp], x095# M4-NEXT: 3 5 1.00 * ld2r { v0.2s, v1.2s }, [sp], x096# M4-NEXT: 3 10 3.00 * ld2 { v0.2s, v1.2s }, [sp], x097# M4-NEXT: 4 6 1.00 * ld2 { v0.d, v1.d }[0], [sp], x098# M4-NEXT: 3 5 1.00 * ld2r { v0.2d, v1.2d }, [sp], x099# M4-NEXT: 3 10 3.00 * ld2 { v0.2d, v1.2d }, [sp], x0100 101# M5-NEXT: 3 7 1.00 * ld2 { v0.s, v1.s }[0], [sp]102# M5-NEXT: 2 6 1.00 * ld2r { v0.2s, v1.2s }, [sp]103# M5-NEXT: 2 11 5.50 * ld2 { v0.2s, v1.2s }, [sp]104# M5-NEXT: 3 7 1.00 * ld2 { v0.d, v1.d }[0], [sp]105# M5-NEXT: 2 6 1.00 * ld2r { v0.2d, v1.2d }, [sp]106# M5-NEXT: 2 11 5.50 * ld2 { v0.2d, v1.2d }, [sp]107# M5-NEXT: 4 7 1.00 * ld2 { v0.s, v1.s }[0], [sp], #8108# M5-NEXT: 3 6 1.00 * ld2r { v0.2s, v1.2s }, [sp], #8109# M5-NEXT: 3 11 5.50 * ld2 { v0.2s, v1.2s }, [sp], #16110# M5-NEXT: 4 7 1.00 * ld2 { v0.d, v1.d }[0], [sp], #16111# M5-NEXT: 3 6 1.00 * ld2r { v0.2d, v1.2d }, [sp], #16112# M5-NEXT: 3 11 5.50 * ld2 { v0.2d, v1.2d }, [sp], #32113# M5-NEXT: 4 7 1.00 * ld2 { v0.s, v1.s }[0], [sp], x0114# M5-NEXT: 3 6 1.00 * ld2r { v0.2s, v1.2s }, [sp], x0115# M5-NEXT: 3 11 5.50 * ld2 { v0.2s, v1.2s }, [sp], x0116# M5-NEXT: 4 7 1.00 * ld2 { v0.d, v1.d }[0], [sp], x0117# M5-NEXT: 3 6 1.00 * ld2r { v0.2d, v1.2d }, [sp], x0118# M5-NEXT: 3 11 5.50 * ld2 { v0.2d, v1.2d }, [sp], x0119