brintos

brintos / llvm-project-archived public Read only

0
0
Text · 7.2 KiB · 16bbd1d Raw
119 lines · plain
1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py2# RUN: llvm-mca -mtriple=aarch64-linux-gnu -mcpu=exynos-m3 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M33# RUN: llvm-mca -mtriple=aarch64-linux-gnu -mcpu=exynos-m4 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M44# RUN: llvm-mca -mtriple=aarch64-linux-gnu -mcpu=exynos-m5 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M55 6ld4	{v0.s, v1.s, v2.s, v3.s}[0], [sp]7ld4r	{v0.2s, v1.2s, v2.2s, v3.2s}, [sp]8ld4	{v0.2s, v1.2s, v2.2s, v3.2s}, [sp]9 10ld4	{v0.d, v1.d, v2.d, v3.d}[0], [sp]11ld4r	{v0.2d, v1.2d, v2.2d, v3.2d}, [sp]12ld4	{v0.2d, v1.2d, v2.2d, v3.2d}, [sp]13 14ld4	{v0.s, v1.s, v2.s, v3.s}[0], [sp], #1615ld4r	{v0.2s, v1.2s, v2.2s, v3.2s}, [sp], #1616ld4	{v0.2s, v1.2s, v2.2s, v3.2s}, [sp], #3217 18ld4	{v0.d, v1.d, v2.d, v3.d}[0], [sp], #3219ld4r	{v0.2d, v1.2d, v2.2d, v3.2d}, [sp], #3220ld4	{v0.2d, v1.2d, v2.2d, v3.2d}, [sp], #6421 22ld4	{v0.s, v1.s, v2.s, v3.s}[0], [sp], x023ld4r	{v0.2s, v1.2s, v2.2s, v3.2s}, [sp], x024ld4	{v0.2s, v1.2s, v2.2s, v3.2s}, [sp], x025 26ld4	{v0.d, v1.d, v2.d, v3.d}[0], [sp], x027ld4r	{v0.2d, v1.2d, v2.2d, v3.2d}, [sp], x028ld4	{v0.2d, v1.2d, v2.2d, v3.2d}, [sp], x029 30# ALL:      Iterations:        10031# ALL-NEXT: Instructions:      180032 33# M3-NEXT:  Total Cycles:      1559834# M4-NEXT:  Total Cycles:      1300435# M5-NEXT:  Total Cycles:      1430436 37# ALL-NEXT: Total uOps:        930038 39# ALL:      Dispatch Width:    640 41# M3-NEXT:  uOps Per Cycle:    0.6042# M3-NEXT:  IPC:               0.1243# M3-NEXT:  Block RThroughput: 108.044 45# M4-NEXT:  uOps Per Cycle:    0.7246# M4-NEXT:  IPC:               0.1447# M4-NEXT:  Block RThroughput: 61.548 49# M5-NEXT:  uOps Per Cycle:    0.6550# M5-NEXT:  IPC:               0.1351# M5-NEXT:  Block RThroughput: 40.552 53# ALL:      Instruction Info:54# ALL-NEXT: [1]: #uOps55# ALL-NEXT: [2]: Latency56# ALL-NEXT: [3]: RThroughput57# ALL-NEXT: [4]: MayLoad58# ALL-NEXT: [5]: MayStore59# ALL-NEXT: [6]: HasSideEffects (U)60 61# ALL:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:62 63# M3-NEXT:   5      9     2.00    *                   ld4	{ v0.s, v1.s, v2.s, v3.s }[0], [sp]64# M3-NEXT:   4      6     2.00    *                   ld4r	{ v0.2s, v1.2s, v2.2s, v3.2s }, [sp]65# M3-NEXT:   4      14    12.00   *                   ld4	{ v0.2s, v1.2s, v2.2s, v3.2s }, [sp]66# M3-NEXT:   6      7     6.00    *                   ld4	{ v0.d, v1.d, v2.d, v3.d }[0], [sp]67# M3-NEXT:   4      6     2.00    *                   ld4r	{ v0.2d, v1.2d, v2.2d, v3.2d }, [sp]68# M3-NEXT:   4      14    12.00   *                   ld4	{ v0.2d, v1.2d, v2.2d, v3.2d }, [sp]69# M3-NEXT:   6      9     2.00    *                   ld4	{ v0.s, v1.s, v2.s, v3.s }[0], [sp], #1670# M3-NEXT:   5      6     2.00    *                   ld4r	{ v0.2s, v1.2s, v2.2s, v3.2s }, [sp], #1671# M3-NEXT:   5      14    12.00   *                   ld4	{ v0.2s, v1.2s, v2.2s, v3.2s }, [sp], #3272# M3-NEXT:   7      7     6.00    *                   ld4	{ v0.d, v1.d, v2.d, v3.d }[0], [sp], #3273# M3-NEXT:   5      6     2.00    *                   ld4r	{ v0.2d, v1.2d, v2.2d, v3.2d }, [sp], #3274# M3-NEXT:   5      14    12.00   *                   ld4	{ v0.2d, v1.2d, v2.2d, v3.2d }, [sp], #6475# M3-NEXT:   6      9     2.00    *                   ld4	{ v0.s, v1.s, v2.s, v3.s }[0], [sp], x076# M3-NEXT:   5      6     2.00    *                   ld4r	{ v0.2s, v1.2s, v2.2s, v3.2s }, [sp], x077# M3-NEXT:   5      14    12.00   *                   ld4	{ v0.2s, v1.2s, v2.2s, v3.2s }, [sp], x078# M3-NEXT:   7      7     6.00    *                   ld4	{ v0.d, v1.d, v2.d, v3.d }[0], [sp], x079# M3-NEXT:   5      6     2.00    *                   ld4r	{ v0.2d, v1.2d, v2.2d, v3.2d }, [sp], x080# M3-NEXT:   5      14    12.00   *                   ld4	{ v0.2d, v1.2d, v2.2d, v3.2d }, [sp], x081 82# M4-NEXT:   5      7     2.00    *                   ld4	{ v0.s, v1.s, v2.s, v3.s }[0], [sp]83# M4-NEXT:   4      6     2.00    *                   ld4r	{ v0.2s, v1.2s, v2.2s, v3.2s }, [sp]84# M4-NEXT:   4      14    6.00    *                   ld4	{ v0.2s, v1.2s, v2.2s, v3.2s }, [sp]85# M4-NEXT:   6      7     3.00    *                   ld4	{ v0.d, v1.d, v2.d, v3.d }[0], [sp]86# M4-NEXT:   4      6     2.00    *                   ld4r	{ v0.2d, v1.2d, v2.2d, v3.2d }, [sp]87# M4-NEXT:   4      14    6.00    *                   ld4	{ v0.2d, v1.2d, v2.2d, v3.2d }, [sp]88# M4-NEXT:   6      7     2.00    *                   ld4	{ v0.s, v1.s, v2.s, v3.s }[0], [sp], #1689# M4-NEXT:   5      6     2.00    *                   ld4r	{ v0.2s, v1.2s, v2.2s, v3.2s }, [sp], #1690# M4-NEXT:   5      14    6.00    *                   ld4	{ v0.2s, v1.2s, v2.2s, v3.2s }, [sp], #3291# M4-NEXT:   7      7     3.00    *                   ld4	{ v0.d, v1.d, v2.d, v3.d }[0], [sp], #3292# M4-NEXT:   5      6     2.00    *                   ld4r	{ v0.2d, v1.2d, v2.2d, v3.2d }, [sp], #3293# M4-NEXT:   5      14    6.00    *                   ld4	{ v0.2d, v1.2d, v2.2d, v3.2d }, [sp], #6494# M4-NEXT:   6      7     2.00    *                   ld4	{ v0.s, v1.s, v2.s, v3.s }[0], [sp], x095# M4-NEXT:   5      6     2.00    *                   ld4r	{ v0.2s, v1.2s, v2.2s, v3.2s }, [sp], x096# M4-NEXT:   5      14    6.00    *                   ld4	{ v0.2s, v1.2s, v2.2s, v3.2s }, [sp], x097# M4-NEXT:   7      7     3.00    *                   ld4	{ v0.d, v1.d, v2.d, v3.d }[0], [sp], x098# M4-NEXT:   5      6     2.00    *                   ld4r	{ v0.2d, v1.2d, v2.2d, v3.2d }, [sp], x099# M4-NEXT:   5      14    6.00    *                   ld4	{ v0.2d, v1.2d, v2.2d, v3.2d }, [sp], x0100 101# M5-NEXT:   5      8     2.00    *                   ld4	{ v0.s, v1.s, v2.s, v3.s }[0], [sp]102# M5-NEXT:   4      7     2.00    *                   ld4r	{ v0.2s, v1.2s, v2.2s, v3.2s }, [sp]103# M5-NEXT:   4      15    4.00    *                   ld4	{ v0.2s, v1.2s, v2.2s, v3.2s }, [sp]104# M5-NEXT:   6      8     2.00    *                   ld4	{ v0.d, v1.d, v2.d, v3.d }[0], [sp]105# M5-NEXT:   4      7     2.00    *                   ld4r	{ v0.2d, v1.2d, v2.2d, v3.2d }, [sp]106# M5-NEXT:   4      15    4.00    *                   ld4	{ v0.2d, v1.2d, v2.2d, v3.2d }, [sp]107# M5-NEXT:   6      8     2.00    *                   ld4	{ v0.s, v1.s, v2.s, v3.s }[0], [sp], #16108# M5-NEXT:   5      7     2.00    *                   ld4r	{ v0.2s, v1.2s, v2.2s, v3.2s }, [sp], #16109# M5-NEXT:   5      15    4.00    *                   ld4	{ v0.2s, v1.2s, v2.2s, v3.2s }, [sp], #32110# M5-NEXT:   7      8     2.00    *                   ld4	{ v0.d, v1.d, v2.d, v3.d }[0], [sp], #32111# M5-NEXT:   5      7     2.00    *                   ld4r	{ v0.2d, v1.2d, v2.2d, v3.2d }, [sp], #32112# M5-NEXT:   5      15    4.00    *                   ld4	{ v0.2d, v1.2d, v2.2d, v3.2d }, [sp], #64113# M5-NEXT:   6      8     2.00    *                   ld4	{ v0.s, v1.s, v2.s, v3.s }[0], [sp], x0114# M5-NEXT:   5      7     2.00    *                   ld4r	{ v0.2s, v1.2s, v2.2s, v3.2s }, [sp], x0115# M5-NEXT:   5      15    4.00    *                   ld4	{ v0.2s, v1.2s, v2.2s, v3.2s }, [sp], x0116# M5-NEXT:   7      8     2.00    *                   ld4	{ v0.d, v1.d, v2.d, v3.d }[0], [sp], x0117# M5-NEXT:   5      7     2.00    *                   ld4r	{ v0.2d, v1.2d, v2.2d, v3.2d }, [sp], x0118# M5-NEXT:   5      15    4.00    *                   ld4	{ v0.2d, v1.2d, v2.2d, v3.2d }, [sp], x0119