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1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py2# RUN: llvm-mca -mtriple=aarch64-linux-gnu -mcpu=exynos-m3 -resource-pressure=false -noalias=false < %s | FileCheck %s -check-prefixes=ALL,M33# RUN: llvm-mca -mtriple=aarch64-linux-gnu -mcpu=exynos-m4 -resource-pressure=false -noalias=false < %s | FileCheck %s -check-prefixes=ALL,M44# RUN: llvm-mca -mtriple=aarch64-linux-gnu -mcpu=exynos-m5 -resource-pressure=false -noalias=false < %s | FileCheck %s -check-prefixes=ALL,M55 6st1 {v0.s}[0], [sp]7st1 {v0.2s}, [sp]8st1 {v0.2s, v1.2s}, [sp]9st1 {v0.2s, v1.2s, v2.2s}, [sp]10st1 {v0.2s, v1.2s, v2.2s, v3.2s}, [sp]11 12st1 {v0.d}[0], [sp]13st1 {v0.2d}, [sp]14st1 {v0.2d, v1.2d}, [sp]15st1 {v0.2d, v1.2d, v2.2d}, [sp]16st1 {v0.2d, v1.2d, v2.2d, v3.2d}, [sp]17 18st1 {v0.s}[0], [sp], #419st1 {v0.2s}, [sp], #820st1 {v0.2s, v1.2s}, [sp], #1621st1 {v0.2s, v1.2s, v2.2s}, [sp], #2422st1 {v0.2s, v1.2s, v2.2s, v3.2s}, [sp], #3223 24st1 {v0.d}[0], [sp], #825st1 {v0.2d}, [sp], #1626st1 {v0.2d, v1.2d}, [sp], #3227st1 {v0.2d, v1.2d, v2.2d}, [sp], #4828st1 {v0.2d, v1.2d, v2.2d, v3.2d}, [sp], #6429 30st1 {v0.s}[0], [sp], x031st1 {v0.2s}, [sp], x032st1 {v0.2s, v1.2s}, [sp], x033st1 {v0.2s, v1.2s, v2.2s}, [sp], x034st1 {v0.2s, v1.2s, v2.2s, v3.2s}, [sp], x035 36st1 {v0.d}[0], [sp], x037st1 {v0.2d}, [sp], x038st1 {v0.2d, v1.2d}, [sp], x039st1 {v0.2d, v1.2d, v2.2d}, [sp], x040st1 {v0.2d, v1.2d, v2.2d, v3.2d}, [sp], x041 42# ALL: Iterations: 10043# ALL-NEXT: Instructions: 300044 45# M3-NEXT: Total Cycles: 1020346# M3-NEXT: Total uOps: 840047 48# M4-NEXT: Total Cycles: 660349# M4-NEXT: Total uOps: 860050 51# M5-NEXT: Total Cycles: 660352# M5-NEXT: Total uOps: 860053 54# ALL: Dispatch Width: 655 56# M3-NEXT: uOps Per Cycle: 0.8257# M3-NEXT: IPC: 0.2958# M3-NEXT: Block RThroughput: 72.059 60# M4-NEXT: uOps Per Cycle: 1.3061# M4-NEXT: IPC: 0.4562# M4-NEXT: Block RThroughput: 33.063 64# M5-NEXT: uOps Per Cycle: 1.3065# M5-NEXT: IPC: 0.4566# M5-NEXT: Block RThroughput: 33.067 68# ALL: Instruction Info:69# ALL-NEXT: [1]: #uOps70# ALL-NEXT: [2]: Latency71# ALL-NEXT: [3]: RThroughput72# ALL-NEXT: [4]: MayLoad73# ALL-NEXT: [5]: MayStore74# ALL-NEXT: [6]: HasSideEffects (U)75 76# ALL: [1] [2] [3] [4] [5] [6] Instructions:77 78# M3-NEXT: 4 7 3.00 * st1 { v0.s }[0], [sp]79# M3-NEXT: 1 1 1.00 * st1 { v0.2s }, [sp]80# M3-NEXT: 2 2 2.00 * st1 { v0.2s, v1.2s }, [sp]81# M3-NEXT: 3 3 3.00 * st1 { v0.2s, v1.2s, v2.2s }, [sp]82# M3-NEXT: 4 4 4.00 * st1 { v0.2s, v1.2s, v2.2s, v3.2s }, [sp]83# M3-NEXT: 4 7 3.00 * st1 { v0.d }[0], [sp]84# M3-NEXT: 1 1 1.00 * st1 { v0.2d }, [sp]85# M3-NEXT: 2 2 2.00 * st1 { v0.2d, v1.2d }, [sp]86# M3-NEXT: 3 3 3.00 * st1 { v0.2d, v1.2d, v2.2d }, [sp]87# M3-NEXT: 4 4 4.00 * st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [sp]88# M3-NEXT: 4 7 3.00 * st1 { v0.s }[0], [sp], #489# M3-NEXT: 1 1 1.00 * st1 { v0.2s }, [sp], #890# M3-NEXT: 2 2 2.00 * st1 { v0.2s, v1.2s }, [sp], #1691# M3-NEXT: 3 3 3.00 * st1 { v0.2s, v1.2s, v2.2s }, [sp], #2492# M3-NEXT: 4 4 4.00 * st1 { v0.2s, v1.2s, v2.2s, v3.2s }, [sp], #3293# M3-NEXT: 4 7 3.00 * st1 { v0.d }[0], [sp], #894# M3-NEXT: 1 1 1.00 * st1 { v0.2d }, [sp], #1695# M3-NEXT: 2 2 2.00 * st1 { v0.2d, v1.2d }, [sp], #3296# M3-NEXT: 3 3 3.00 * st1 { v0.2d, v1.2d, v2.2d }, [sp], #4897# M3-NEXT: 4 4 4.00 * st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [sp], #6498# M3-NEXT: 4 7 3.00 * st1 { v0.s }[0], [sp], x099# M3-NEXT: 1 1 1.00 * st1 { v0.2s }, [sp], x0100# M3-NEXT: 2 2 2.00 * st1 { v0.2s, v1.2s }, [sp], x0101# M3-NEXT: 3 3 3.00 * st1 { v0.2s, v1.2s, v2.2s }, [sp], x0102# M3-NEXT: 4 4 4.00 * st1 { v0.2s, v1.2s, v2.2s, v3.2s }, [sp], x0103# M3-NEXT: 4 7 3.00 * st1 { v0.d }[0], [sp], x0104# M3-NEXT: 1 1 1.00 * st1 { v0.2d }, [sp], x0105# M3-NEXT: 2 2 2.00 * st1 { v0.2d, v1.2d }, [sp], x0106# M3-NEXT: 3 3 3.00 * st1 { v0.2d, v1.2d, v2.2d }, [sp], x0107# M3-NEXT: 4 4 4.00 * st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [sp], x0108 109# M4-NEXT: 1 1 0.50 * st1 { v0.s }[0], [sp]110# M4-NEXT: 1 1 0.50 * st1 { v0.2s }, [sp]111# M4-NEXT: 2 2 1.00 * st1 { v0.2s, v1.2s }, [sp]112# M4-NEXT: 3 3 1.50 * st1 { v0.2s, v1.2s, v2.2s }, [sp]113# M4-NEXT: 4 4 2.00 * st1 { v0.2s, v1.2s, v2.2s, v3.2s }, [sp]114# M4-NEXT: 1 1 0.50 * st1 { v0.d }[0], [sp]115# M4-NEXT: 1 1 0.50 * st1 { v0.2d }, [sp]116# M4-NEXT: 2 2 1.00 * st1 { v0.2d, v1.2d }, [sp]117# M4-NEXT: 3 3 1.50 * st1 { v0.2d, v1.2d, v2.2d }, [sp]118# M4-NEXT: 4 4 2.00 * st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [sp]119# M4-NEXT: 2 1 0.50 * st1 { v0.s }[0], [sp], #4120# M4-NEXT: 2 1 0.50 * st1 { v0.2s }, [sp], #8121# M4-NEXT: 3 2 1.00 * st1 { v0.2s, v1.2s }, [sp], #16122# M4-NEXT: 4 3 1.50 * st1 { v0.2s, v1.2s, v2.2s }, [sp], #24123# M4-NEXT: 5 4 2.00 * st1 { v0.2s, v1.2s, v2.2s, v3.2s }, [sp], #32124# M4-NEXT: 2 1 0.50 * st1 { v0.d }[0], [sp], #8125# M4-NEXT: 2 1 0.50 * st1 { v0.2d }, [sp], #16126# M4-NEXT: 3 2 1.00 * st1 { v0.2d, v1.2d }, [sp], #32127# M4-NEXT: 4 3 1.50 * st1 { v0.2d, v1.2d, v2.2d }, [sp], #48128# M4-NEXT: 5 4 2.00 * st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [sp], #64129# M4-NEXT: 2 1 0.50 * st1 { v0.s }[0], [sp], x0130# M4-NEXT: 2 1 0.50 * st1 { v0.2s }, [sp], x0131# M4-NEXT: 3 2 1.00 * st1 { v0.2s, v1.2s }, [sp], x0132# M4-NEXT: 4 3 1.50 * st1 { v0.2s, v1.2s, v2.2s }, [sp], x0133# M4-NEXT: 5 4 2.00 * st1 { v0.2s, v1.2s, v2.2s, v3.2s }, [sp], x0134# M4-NEXT: 2 1 0.50 * st1 { v0.d }[0], [sp], x0135# M4-NEXT: 2 1 0.50 * st1 { v0.2d }, [sp], x0136# M4-NEXT: 3 2 1.00 * st1 { v0.2d, v1.2d }, [sp], x0137# M4-NEXT: 4 3 1.50 * st1 { v0.2d, v1.2d, v2.2d }, [sp], x0138# M4-NEXT: 5 4 2.00 * st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [sp], x0139 140# M5-NEXT: 1 1 0.50 * st1 { v0.s }[0], [sp]141# M5-NEXT: 1 1 0.50 * st1 { v0.2s }, [sp]142# M5-NEXT: 2 2 1.00 * st1 { v0.2s, v1.2s }, [sp]143# M5-NEXT: 3 3 1.50 * st1 { v0.2s, v1.2s, v2.2s }, [sp]144# M5-NEXT: 4 4 2.00 * st1 { v0.2s, v1.2s, v2.2s, v3.2s }, [sp]145# M5-NEXT: 1 1 0.50 * st1 { v0.d }[0], [sp]146# M5-NEXT: 1 1 0.50 * st1 { v0.2d }, [sp]147# M5-NEXT: 2 2 1.00 * st1 { v0.2d, v1.2d }, [sp]148# M5-NEXT: 3 3 1.50 * st1 { v0.2d, v1.2d, v2.2d }, [sp]149# M5-NEXT: 4 4 2.00 * st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [sp]150# M5-NEXT: 2 1 0.50 * st1 { v0.s }[0], [sp], #4151# M5-NEXT: 2 1 0.50 * st1 { v0.2s }, [sp], #8152# M5-NEXT: 3 2 1.00 * st1 { v0.2s, v1.2s }, [sp], #16153# M5-NEXT: 4 3 1.50 * st1 { v0.2s, v1.2s, v2.2s }, [sp], #24154# M5-NEXT: 5 4 2.00 * st1 { v0.2s, v1.2s, v2.2s, v3.2s }, [sp], #32155# M5-NEXT: 2 1 0.50 * st1 { v0.d }[0], [sp], #8156# M5-NEXT: 2 1 0.50 * st1 { v0.2d }, [sp], #16157# M5-NEXT: 3 2 1.00 * st1 { v0.2d, v1.2d }, [sp], #32158# M5-NEXT: 4 3 1.50 * st1 { v0.2d, v1.2d, v2.2d }, [sp], #48159# M5-NEXT: 5 4 2.00 * st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [sp], #64160# M5-NEXT: 2 1 0.50 * st1 { v0.s }[0], [sp], x0161# M5-NEXT: 2 1 0.50 * st1 { v0.2s }, [sp], x0162# M5-NEXT: 3 2 1.00 * st1 { v0.2s, v1.2s }, [sp], x0163# M5-NEXT: 4 3 1.50 * st1 { v0.2s, v1.2s, v2.2s }, [sp], x0164# M5-NEXT: 5 4 2.00 * st1 { v0.2s, v1.2s, v2.2s, v3.2s }, [sp], x0165# M5-NEXT: 2 1 0.50 * st1 { v0.d }[0], [sp], x0166# M5-NEXT: 2 1 0.50 * st1 { v0.2d }, [sp], x0167# M5-NEXT: 3 2 1.00 * st1 { v0.2d, v1.2d }, [sp], x0168# M5-NEXT: 4 3 1.50 * st1 { v0.2d, v1.2d, v2.2d }, [sp], x0169# M5-NEXT: 5 4 2.00 * st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [sp], x0170