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1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py2# RUN: llvm-mca -mtriple=aarch64-linux-gnu -mcpu=exynos-m3 -resource-pressure=false -noalias=false < %s | FileCheck %s -check-prefixes=ALL,M33# RUN: llvm-mca -mtriple=aarch64-linux-gnu -mcpu=exynos-m4 -resource-pressure=false -noalias=false < %s | FileCheck %s -check-prefixes=ALL,M44# RUN: llvm-mca -mtriple=aarch64-linux-gnu -mcpu=exynos-m5 -resource-pressure=false -noalias=false < %s | FileCheck %s -check-prefixes=ALL,M55 6st2 {v0.s, v1.s}[0], [sp]7st2 {v0.2s, v1.2s}, [sp]8 9st2 {v0.d, v1.d}[0], [sp]10st2 {v0.2d, v1.2d}, [sp]11 12st2 {v0.s, v1.s}[0], [sp], #813st2 {v0.2s, v1.2s}, [sp], #1614 15st2 {v0.d, v1.d}[0], [sp], #1616st2 {v0.2d, v1.2d}, [sp], #3217 18st2 {v0.s, v1.s}[0], [sp], x019st2 {v0.2s, v1.2s}, [sp], x020 21st2 {v0.d, v1.d}[0], [sp], x022st2 {v0.2d, v1.2d}, [sp], x023 24# ALL: Iterations: 10025# ALL-NEXT: Instructions: 120026 27# M3-NEXT: Total Cycles: 870328# M3-NEXT: Total uOps: 540029 30# M4-NEXT: Total Cycles: 240331# M4-NEXT: Total uOps: 230032 33# M5-NEXT: Total Cycles: 240334# M5-NEXT: Total uOps: 200035 36# ALL: Dispatch Width: 637 38# M3-NEXT: uOps Per Cycle: 0.6239# M3-NEXT: IPC: 0.1440# M3-NEXT: Block RThroughput: 40.541 42# M4-NEXT: uOps Per Cycle: 0.9643# M4-NEXT: IPC: 0.5044# M4-NEXT: Block RThroughput: 7.545 46# M5-NEXT: uOps Per Cycle: 0.8347# M5-NEXT: IPC: 0.5048# M5-NEXT: Block RThroughput: 7.549 50# ALL: Instruction Info:51# ALL-NEXT: [1]: #uOps52# ALL-NEXT: [2]: Latency53# ALL-NEXT: [3]: RThroughput54# ALL-NEXT: [4]: MayLoad55# ALL-NEXT: [5]: MayStore56# ALL-NEXT: [6]: HasSideEffects (U)57 58# ALL: [1] [2] [3] [4] [5] [6] Instructions:59 60# M3-NEXT: 4 7 3.00 * st2 { v0.s, v1.s }[0], [sp]61# M3-NEXT: 4 7 3.00 * st2 { v0.2s, v1.2s }, [sp]62# M3-NEXT: 4 7 3.00 * st2 { v0.d, v1.d }[0], [sp]63# M3-NEXT: 6 8 4.50 * st2 { v0.2d, v1.2d }, [sp]64# M3-NEXT: 4 7 3.00 * st2 { v0.s, v1.s }[0], [sp], #865# M3-NEXT: 4 7 3.00 * st2 { v0.2s, v1.2s }, [sp], #1666# M3-NEXT: 4 7 3.00 * st2 { v0.d, v1.d }[0], [sp], #1667# M3-NEXT: 6 8 4.50 * st2 { v0.2d, v1.2d }, [sp], #3268# M3-NEXT: 4 7 3.00 * st2 { v0.s, v1.s }[0], [sp], x069# M3-NEXT: 4 7 3.00 * st2 { v0.2s, v1.2s }, [sp], x070# M3-NEXT: 4 7 3.00 * st2 { v0.d, v1.d }[0], [sp], x071# M3-NEXT: 6 8 4.50 * st2 { v0.2d, v1.2d }, [sp], x072 73# M4-NEXT: 1 2 0.50 * st2 { v0.s, v1.s }[0], [sp]74# M4-NEXT: 1 2 0.50 * st2 { v0.2s, v1.2s }, [sp]75# M4-NEXT: 1 2 0.50 * st2 { v0.d, v1.d }[0], [sp]76# M4-NEXT: 2 2 1.00 * st2 { v0.2d, v1.2d }, [sp]77# M4-NEXT: 2 2 0.50 * st2 { v0.s, v1.s }[0], [sp], #878# M4-NEXT: 2 2 0.50 * st2 { v0.2s, v1.2s }, [sp], #1679# M4-NEXT: 2 2 0.50 * st2 { v0.d, v1.d }[0], [sp], #1680# M4-NEXT: 3 2 1.00 * st2 { v0.2d, v1.2d }, [sp], #3281# M4-NEXT: 2 2 0.50 * st2 { v0.s, v1.s }[0], [sp], x082# M4-NEXT: 2 2 0.50 * st2 { v0.2s, v1.2s }, [sp], x083# M4-NEXT: 2 2 0.50 * st2 { v0.d, v1.d }[0], [sp], x084# M4-NEXT: 3 2 1.00 * st2 { v0.2d, v1.2d }, [sp], x085 86# M5-NEXT: 1 2 0.50 * st2 { v0.s, v1.s }[0], [sp]87# M5-NEXT: 1 2 0.50 * st2 { v0.2s, v1.2s }, [sp]88# M5-NEXT: 1 2 0.50 * st2 { v0.d, v1.d }[0], [sp]89# M5-NEXT: 1 2 1.00 * st2 { v0.2d, v1.2d }, [sp]90# M5-NEXT: 2 2 0.50 * st2 { v0.s, v1.s }[0], [sp], #891# M5-NEXT: 2 2 0.50 * st2 { v0.2s, v1.2s }, [sp], #1692# M5-NEXT: 2 2 0.50 * st2 { v0.d, v1.d }[0], [sp], #1693# M5-NEXT: 2 2 1.00 * st2 { v0.2d, v1.2d }, [sp], #3294# M5-NEXT: 2 2 0.50 * st2 { v0.s, v1.s }[0], [sp], x095# M5-NEXT: 2 2 0.50 * st2 { v0.2s, v1.2s }, [sp], x096# M5-NEXT: 2 2 0.50 * st2 { v0.d, v1.d }[0], [sp], x097# M5-NEXT: 2 2 1.00 * st2 { v0.2d, v1.2d }, [sp], x098