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1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py2# RUN: llvm-mca -march=aarch64 -mcpu=exynos-m3 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,EM33# RUN: llvm-mca -march=aarch64 -mcpu=exynos-m4 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,EM44# RUN: llvm-mca -march=aarch64 -mcpu=exynos-m5 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,EM55 6sdiv w0, w1, w27udiv x1, x2, x38 9mul w2, w3, w410msub x3, x4, x5, x611 12smull x4, w5, w613umulh x5, x6, x714 15# ALL: Iterations: 10016# ALL-NEXT: Instructions: 60017 18# EM3-NEXT: Total Cycles: 330519# EM4-NEXT: Total Cycles: 330320# EM5-NEXT: Total Cycles: 260321 22# ALL-NEXT: Total uOps: 60023 24# ALL: Dispatch Width: 625 26# EM3-NEXT: uOps Per Cycle: 0.1827# EM3-NEXT: IPC: 0.1828# EM3-NEXT: Block RThroughput: 33.029 30# EM4-NEXT: uOps Per Cycle: 0.1831# EM4-NEXT: IPC: 0.1832# EM4-NEXT: Block RThroughput: 33.033 34# EM5-NEXT: uOps Per Cycle: 0.2335# EM5-NEXT: IPC: 0.2336# EM5-NEXT: Block RThroughput: 26.037 38# ALL: Instruction Info:39# ALL-NEXT: [1]: #uOps40# ALL-NEXT: [2]: Latency41# ALL-NEXT: [3]: RThroughput42# ALL-NEXT: [4]: MayLoad43# ALL-NEXT: [5]: MayStore44# ALL-NEXT: [6]: HasSideEffects (U)45 46# ALL: [1] [2] [3] [4] [5] [6] Instructions:47 48# EM3-NEXT: 1 12 12.00 sdiv w0, w1, w249# EM3-NEXT: 1 21 21.00 udiv x1, x2, x350# EM3-NEXT: 1 3 0.50 mul w2, w3, w451# EM3-NEXT: 1 4 1.00 msub x3, x4, x5, x652# EM3-NEXT: 1 3 0.50 smull x4, w5, w653# EM3-NEXT: 1 4 1.00 umulh x5, x6, x754 55# EM4-NEXT: 1 12 12.00 sdiv w0, w1, w256# EM4-NEXT: 1 21 21.00 udiv x1, x2, x357# EM4-NEXT: 1 3 0.50 mul w2, w3, w458# EM4-NEXT: 1 4 1.00 msub x3, x4, x5, x659# EM4-NEXT: 1 3 0.50 smull x4, w5, w660# EM4-NEXT: 1 4 1.00 umulh x5, x6, x761 62# EM5-NEXT: 1 10 10.00 sdiv w0, w1, w263# EM5-NEXT: 1 16 16.00 udiv x1, x2, x364# EM5-NEXT: 1 2 0.50 mul w2, w3, w465# EM5-NEXT: 1 3 1.00 msub x3, x4, x5, x666# EM5-NEXT: 1 2 0.50 smull x4, w5, w667# EM5-NEXT: 1 3 1.00 umulh x5, x6, x768