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1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py2# RUN: llvm-mca -march=aarch64 -mcpu=exynos-m3 -resource-pressure=false -skip-unsupported-instructions=parse-failure < %s | FileCheck %s -check-prefixes=ALL,EM33# RUN: llvm-mca -march=aarch64 -mcpu=exynos-m4 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,EM44# RUN: llvm-mca -march=aarch64 -mcpu=exynos-m5 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,EM55 6fdiv h0, h1, h27fdiv s1, s2, s38fdiv d2, d3, d49 10fmul h3, h4, h511fmul s4, s5, s612fmul d5, d6, d713 14fmadd h6, h7, h8, h915fmadd s7, s8, s9, s1016fmadd d8, d9, d10, d1117 18fsqrt h9, h1019fsqrt s10, s1120fsqrt d11, d1221 22# ALL: Iterations: 10023 24# EM3-NEXT: Instructions: 80025# EM3-NEXT: Total Cycles: 450326# EM3-NEXT: Total uOps: 80027 28# EM4-NEXT: Instructions: 120029# EM4-NEXT: Total Cycles: 57230# EM4-NEXT: Total uOps: 120031 32# EM5-NEXT: Instructions: 120033# EM5-NEXT: Total Cycles: 43434# EM5-NEXT: Total uOps: 120035 36# ALL: Dispatch Width: 637 38# EM3-NEXT: uOps Per Cycle: 0.1839# EM3-NEXT: IPC: 0.1840# EM3-NEXT: Block RThroughput: 45.041 42# EM4-NEXT: uOps Per Cycle: 2.1043# EM4-NEXT: IPC: 2.1044# EM4-NEXT: Block RThroughput: 4.045 46# EM5-NEXT: uOps Per Cycle: 2.7647# EM5-NEXT: IPC: 2.7648# EM5-NEXT: Block RThroughput: 4.049 50# ALL: Instruction Info:51# ALL-NEXT: [1]: #uOps52# ALL-NEXT: [2]: Latency53# ALL-NEXT: [3]: RThroughput54# ALL-NEXT: [4]: MayLoad55# ALL-NEXT: [5]: MayStore56# ALL-NEXT: [6]: HasSideEffects (U)57 58# EM3: [1] [2] [3] [4] [5] [6] Instructions:59# EM3-NEXT: 1 7 2.00 fdiv s1, s2, s360# EM3-NEXT: 1 12 3.25 fdiv d2, d3, d461# EM3-NEXT: 1 3 0.33 fmul s4, s5, s662# EM3-NEXT: 1 3 0.33 fmul d5, d6, d763# EM3-NEXT: 1 4 0.33 fmadd s7, s8, s9, s1064# EM3-NEXT: 1 4 0.33 fmadd d8, d9, d10, d1165# EM3-NEXT: 1 18 19.00 fsqrt s10, s1166# EM3-NEXT: 1 25 26.00 fsqrt d11, d1267 68# EM4: [1] [2] [3] [4] [5] [6] Instructions:69# EM4-NEXT: 1 7 3.00 fdiv h0, h1, h270# EM4-NEXT: 1 7 1.50 fdiv s1, s2, s371# EM4-NEXT: 1 12 2.25 fdiv d2, d3, d472# EM4-NEXT: 1 3 0.50 fmul h3, h4, h573# EM4-NEXT: 1 3 0.33 fmul s4, s5, s674# EM4-NEXT: 1 3 0.33 fmul d5, d6, d775# EM4-NEXT: 1 4 0.50 fmadd h6, h7, h8, h976# EM4-NEXT: 1 4 0.33 fmadd s7, s8, s9, s1077# EM4-NEXT: 1 4 0.33 fmadd d8, d9, d10, d1178# EM4-NEXT: 1 7 3.00 fsqrt h9, h1079# EM4-NEXT: 1 8 1.75 fsqrt s10, s1180# EM4-NEXT: 1 12 2.25 fsqrt d11, d1281 82# EM5: [1] [2] [3] [4] [5] [6] Instructions:83# EM5-NEXT: 1 5 0.50 fdiv h0, h1, h284# EM5-NEXT: 1 7 1.00 fdiv s1, s2, s385# EM5-NEXT: 1 12 2.25 fdiv d2, d3, d486# EM5-NEXT: 1 3 0.33 fmul h3, h4, h587# EM5-NEXT: 1 3 0.33 fmul s4, s5, s688# EM5-NEXT: 1 3 0.33 fmul d5, d6, d789# EM5-NEXT: 1 4 0.33 fmadd h6, h7, h8, h990# EM5-NEXT: 1 4 0.33 fmadd s7, s8, s9, s1091# EM5-NEXT: 1 4 0.33 fmadd d8, d9, d10, d1192# EM5-NEXT: 1 5 0.50 fsqrt h9, h1093# EM5-NEXT: 1 8 1.25 fsqrt s10, s1194# EM5-NEXT: 1 12 2.25 fsqrt d11, d1295