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1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py2# RUN: llvm-mca -march=aarch64 -mcpu=exynos-m3 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M33# RUN: llvm-mca -march=aarch64 -mcpu=exynos-m4 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M44# RUN: llvm-mca -march=aarch64 -mcpu=exynos-m5 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M55 6ldr s0, 1f7ldr q0, 1f8 9ldur d0, [sp, #2]10ldur q0, [sp, #16]11 12ldr b0, [sp], #113ldr q0, [sp], #1614 15ldr h0, [sp, #2]!16ldr q0, [sp, #16]!17 18ldr s0, [sp, #4]19ldr q0, [sp, #16]20 21ldr d0, [sp, x0, lsl #3]22ldr q0, [sp, x0, lsl #4]23 24ldr b0, [sp, x0]25ldr q0, [sp, x0]26 27ldr h0, [sp, w0, sxtw #1]28ldr q0, [sp, w0, uxtw #4]29 30ldr s0, [sp, w0, sxtw]31ldr q0, [sp, w0, uxtw]32 33ldp d0, d1, [sp], #1634ldp q0, q1, [sp], #3235 36ldp s0, s1, [sp, #8]!37ldp q0, q1, [sp, #32]!38 39ldp d0, d1, [sp, #16]40ldp q0, q1, [sp, #32]41 421:43 44# ALL: Iterations: 10045# ALL-NEXT: Instructions: 240046 47# M3-NEXT: Total Cycles: 470848# M3-NEXT: Total uOps: 320049 50# M4-NEXT: Total Cycles: 470851# M4-NEXT: Total uOps: 320052 53# M5-NEXT: Total Cycles: 550954# M5-NEXT: Total uOps: 330055 56# ALL: Dispatch Width: 657 58# M3-NEXT: uOps Per Cycle: 0.6859# M3-NEXT: IPC: 0.5160# M3-NEXT: Block RThroughput: 13.561 62# M4-NEXT: uOps Per Cycle: 0.6863# M4-NEXT: IPC: 0.5164# M4-NEXT: Block RThroughput: 13.065 66# M5-NEXT: uOps Per Cycle: 0.6067# M5-NEXT: IPC: 0.4468# M5-NEXT: Block RThroughput: 13.569 70# ALL: Instruction Info:71# ALL-NEXT: [1]: #uOps72# ALL-NEXT: [2]: Latency73# ALL-NEXT: [3]: RThroughput74# ALL-NEXT: [4]: MayLoad75# ALL-NEXT: [5]: MayStore76# ALL-NEXT: [6]: HasSideEffects (U)77 78# ALL: [1] [2] [3] [4] [5] [6] Instructions:79 80# M3-NEXT: 1 5 0.50 * ldr s0, {{\.?}}Ltmp081# M3-NEXT: 1 5 0.50 * ldr q0, {{\.?}}Ltmp082# M3-NEXT: 1 5 0.50 * ldur d0, [sp, #2]83# M3-NEXT: 1 5 0.50 * ldur q0, [sp, #16]84# M3-NEXT: 1 5 0.50 * ldr b0, [sp], #185# M3-NEXT: 1 5 0.50 * ldr q0, [sp], #1686# M3-NEXT: 1 5 0.50 * ldr h0, [sp, #2]!87# M3-NEXT: 1 5 0.50 * ldr q0, [sp, #16]!88# M3-NEXT: 1 5 0.50 * ldr s0, [sp, #4]89# M3-NEXT: 1 5 0.50 * ldr q0, [sp, #16]90# M3-NEXT: 1 5 0.50 * ldr d0, [sp, x0, lsl #3]91# M3-NEXT: 2 6 0.50 * ldr q0, [sp, x0, lsl #4]92# M3-NEXT: 1 5 0.50 * ldr b0, [sp, x0]93# M3-NEXT: 1 5 0.50 * ldr q0, [sp, x0]94# M3-NEXT: 2 6 0.50 * ldr h0, [sp, w0, sxtw #1]95# M3-NEXT: 2 6 0.50 * ldr q0, [sp, w0, uxtw #4]96# M3-NEXT: 2 6 0.50 * ldr s0, [sp, w0, sxtw]97# M3-NEXT: 1 5 0.50 * ldr q0, [sp, w0, uxtw]98# M3-NEXT: 2 5 0.50 * ldp d0, d1, [sp], #1699# M3-NEXT: 2 5 1.00 * ldp q0, q1, [sp], #32100# M3-NEXT: 2 5 0.50 * ldp s0, s1, [sp, #8]!101# M3-NEXT: 2 5 1.00 * ldp q0, q1, [sp, #32]!102# M3-NEXT: 1 5 0.50 * ldp d0, d1, [sp, #16]103# M3-NEXT: 1 5 1.00 * ldp q0, q1, [sp, #32]104 105# M4-NEXT: 1 5 0.50 * ldr s0, {{\.?}}Ltmp0106# M4-NEXT: 1 5 0.50 * ldr q0, {{\.?}}Ltmp0107# M4-NEXT: 1 5 0.50 * ldur d0, [sp, #2]108# M4-NEXT: 1 5 0.50 * ldur q0, [sp, #16]109# M4-NEXT: 1 5 0.50 * ldr b0, [sp], #1110# M4-NEXT: 1 5 0.50 * ldr q0, [sp], #16111# M4-NEXT: 1 5 0.50 * ldr h0, [sp, #2]!112# M4-NEXT: 1 5 0.50 * ldr q0, [sp, #16]!113# M4-NEXT: 1 5 0.50 * ldr s0, [sp, #4]114# M4-NEXT: 1 5 0.50 * ldr q0, [sp, #16]115# M4-NEXT: 1 5 0.50 * ldr d0, [sp, x0, lsl #3]116# M4-NEXT: 2 6 0.50 * ldr q0, [sp, x0, lsl #4]117# M4-NEXT: 1 5 0.50 * ldr b0, [sp, x0]118# M4-NEXT: 1 5 0.50 * ldr q0, [sp, x0]119# M4-NEXT: 2 6 0.50 * ldr h0, [sp, w0, sxtw #1]120# M4-NEXT: 2 6 0.50 * ldr q0, [sp, w0, uxtw #4]121# M4-NEXT: 2 6 0.50 * ldr s0, [sp, w0, sxtw]122# M4-NEXT: 2 6 0.50 * ldr q0, [sp, w0, uxtw]123# M4-NEXT: 1 5 0.50 * ldp d0, d1, [sp], #16124# M4-NEXT: 2 5 0.50 * ldp q0, q1, [sp], #32125# M4-NEXT: 2 5 0.50 * ldp s0, s1, [sp, #8]!126# M4-NEXT: 2 5 1.00 * ldp q0, q1, [sp, #32]!127# M4-NEXT: 1 5 0.50 * ldp d0, d1, [sp, #16]128# M4-NEXT: 1 5 1.00 * ldp q0, q1, [sp, #32]129 130# M5-NEXT: 1 6 0.50 * ldr s0, {{\.?}}Ltmp0131# M5-NEXT: 1 6 0.50 * ldr q0, {{\.?}}Ltmp0132# M5-NEXT: 1 6 0.50 * ldur d0, [sp, #2]133# M5-NEXT: 1 6 0.50 * ldur q0, [sp, #16]134# M5-NEXT: 1 6 0.50 * ldr b0, [sp], #1135# M5-NEXT: 1 6 0.50 * ldr q0, [sp], #16136# M5-NEXT: 1 6 0.50 * ldr h0, [sp, #2]!137# M5-NEXT: 1 6 0.50 * ldr q0, [sp, #16]!138# M5-NEXT: 1 6 0.50 * ldr s0, [sp, #4]139# M5-NEXT: 1 6 0.50 * ldr q0, [sp, #16]140# M5-NEXT: 1 6 0.50 * ldr d0, [sp, x0, lsl #3]141# M5-NEXT: 2 7 0.50 * ldr q0, [sp, x0, lsl #4]142# M5-NEXT: 1 6 0.50 * ldr b0, [sp, x0]143# M5-NEXT: 1 6 0.50 * ldr q0, [sp, x0]144# M5-NEXT: 2 7 0.50 * ldr h0, [sp, w0, sxtw #1]145# M5-NEXT: 2 7 0.50 * ldr q0, [sp, w0, uxtw #4]146# M5-NEXT: 2 7 0.50 * ldr s0, [sp, w0, sxtw]147# M5-NEXT: 2 7 0.50 * ldr q0, [sp, w0, uxtw]148# M5-NEXT: 2 6 0.50 * ldp d0, d1, [sp], #16149# M5-NEXT: 2 6 1.00 * ldp q0, q1, [sp], #32150# M5-NEXT: 2 6 0.50 * ldp s0, s1, [sp, #8]!151# M5-NEXT: 2 6 1.00 * ldp q0, q1, [sp, #32]!152# M5-NEXT: 1 6 0.50 * ldp d0, d1, [sp, #16]153# M5-NEXT: 1 6 1.00 * ldp q0, q1, [sp, #32]154