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1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py2# RUN: llvm-mca -march=aarch64 -mcpu=exynos-m3 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,EM33# RUN: llvm-mca -march=aarch64 -mcpu=exynos-m4 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,EM44# RUN: llvm-mca -march=aarch64 -mcpu=exynos-m5 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,EM55 6 adds w0, w1, w2, lsl #07 sub x3, x4, x5, lsr #18 ands x6, x7, x8, lsl #29 orr w9, w10, w11, asr #310 adds w12, w13, w14, lsl #411 sub x15, x16, x17, lsr #612 ands x18, x19, x20, lsl #813 eor w21, w22, w23, asr #1014 15# ALL: Iterations: 10016# ALL-NEXT: Instructions: 80017 18# EM3-NEXT: Total Cycles: 35419# EM4-NEXT: Total Cycles: 32920# EM5-NEXT: Total Cycles: 22021 22# ALL-NEXT: Total uOps: 80023 24# EM3: Dispatch Width: 625# EM3-NEXT: uOps Per Cycle: 2.2626# EM3-NEXT: IPC: 2.2627# EM3-NEXT: Block RThroughput: 3.528 29# EM4: Dispatch Width: 630# EM4-NEXT: uOps Per Cycle: 2.4331# EM4-NEXT: IPC: 2.4332# EM4-NEXT: Block RThroughput: 3.333 34# EM5: Dispatch Width: 635# EM5-NEXT: uOps Per Cycle: 3.6436# EM5-NEXT: IPC: 3.6437# EM5-NEXT: Block RThroughput: 1.538 39# ALL: Instruction Info:40# ALL-NEXT: [1]: #uOps41# ALL-NEXT: [2]: Latency42# ALL-NEXT: [3]: RThroughput43# ALL-NEXT: [4]: MayLoad44# ALL-NEXT: [5]: MayStore45# ALL-NEXT: [6]: HasSideEffects (U)46 47# ALL: [1] [2] [3] [4] [5] [6] Instructions:48 49# EM3-NEXT: 1 1 0.25 adds w0, w1, w250# EM3-NEXT: 1 2 0.50 sub x3, x4, x5, lsr #151# EM3-NEXT: 1 1 0.25 ands x6, x7, x8, lsl #252# EM3-NEXT: 1 2 0.50 orr w9, w10, w11, asr #353# EM3-NEXT: 1 2 0.50 adds w12, w13, w14, lsl #454# EM3-NEXT: 1 2 0.50 sub x15, x16, x17, lsr #655# EM3-NEXT: 1 2 0.50 ands x18, x19, x20, lsl #856# EM3-NEXT: 1 2 0.50 eor w21, w22, w23, asr #1057 58# EM4-NEXT: 1 1 0.25 adds w0, w1, w259# EM4-NEXT: 1 2 0.50 sub x3, x4, x5, lsr #160# EM4-NEXT: 1 1 0.25 ands x6, x7, x8, lsl #261# EM4-NEXT: 1 2 0.50 orr w9, w10, w11, asr #362# EM4-NEXT: 1 2 0.50 adds w12, w13, w14, lsl #463# EM4-NEXT: 1 2 0.50 sub x15, x16, x17, lsr #664# EM4-NEXT: 1 1 0.25 ands x18, x19, x20, lsl #865# EM4-NEXT: 1 2 0.50 eor w21, w22, w23, asr #1066 67# EM5-NEXT: 1 1 0.17 adds w0, w1, w268# EM5-NEXT: 1 2 0.50 sub x3, x4, x5, lsr #169# EM5-NEXT: 1 1 0.25 ands x6, x7, x8, lsl #270# EM5-NEXT: 1 2 0.33 orr w9, w10, w11, asr #371# EM5-NEXT: 1 2 0.33 adds w12, w13, w14, lsl #472# EM5-NEXT: 1 2 0.50 sub x15, x16, x17, lsr #673# EM5-NEXT: 1 1 0.25 ands x18, x19, x20, lsl #874# EM5-NEXT: 1 2 0.33 eor w21, w22, w23, asr #1075