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1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py2# RUN: llvm-mca -mtriple=riscv64 -mcpu=andes-nx45 -mattr=+b,+zbc -timeline -iterations=1 < %s | FileCheck %s3 4# Two ALUs without dependency can be dispatched in the same cycle.5add a0, a0, a06sub a1, a1, a17 8# Otherwise, they can't be dispatched in the same cycle.9addw a0, a0, a010subw a0, a0, a011 12// ALU and Shift13slli a0, a0, 414slliw a0, a0, 415srl a0, a0, a016srlw a0, a0, a017 18// MDU19mul a0, a0, a020mulw a0, a0, a021div a0, a0, a022divw a0, a0, a023 24// Memory25lb a0, 4(a1)26lh a0, 4(a1)27lw a0, 4(a1)28ld a0, 4(a1)29 30flw fa0, 4(a1)31fld fa0, 4(a1)32 33sb a0, 4(a1)34sh a0, 4(a1)35sw a0, 4(a1)36sd a0, 4(a1)37 38// Atomic Memory39amoswap.w a0, a1, (a0)40amoswap.d a0, a1, (a0)41lr.w a0, (a0)42lr.d a0, (a0)43sc.w a0, a1, (a0)44sc.d a0, a1, (a0)45 46// CSR47csrrw a0, mstatus, zero48 49// Bitmanip50sh1add a0, a0, a051sh1add.uw a0, a0, a052rori a0, a0, 453roriw a0, a0, 454rol a0, a0, a055rolw a0, a0, a056clz a0, a057clzw a0, a058clmul a0, a0, a059bclri a0, a0, 460bclr a0, a0, a061bexti a0, a0, 462bext a0, a0, a063 64# CHECK: Iterations: 165# CHECK-NEXT: Instructions: 4266# CHECK-NEXT: Total Cycles: 15867# CHECK-NEXT: Total uOps: 4268 69# CHECK: Dispatch Width: 270# CHECK-NEXT: uOps Per Cycle: 0.2771# CHECK-NEXT: IPC: 0.2772# CHECK-NEXT: Block RThroughput: 80.073 74# CHECK: Instruction Info:75# CHECK-NEXT: [1]: #uOps76# CHECK-NEXT: [2]: Latency77# CHECK-NEXT: [3]: RThroughput78# CHECK-NEXT: [4]: MayLoad79# CHECK-NEXT: [5]: MayStore80# CHECK-NEXT: [6]: HasSideEffects (U)81 82# CHECK: [1] [2] [3] [4] [5] [6] Instructions:83# CHECK-NEXT: 1 1 0.50 add a0, a0, a084# CHECK-NEXT: 1 1 0.50 sub a1, a1, a185# CHECK-NEXT: 1 1 0.50 addw a0, a0, a086# CHECK-NEXT: 1 1 0.50 subw a0, a0, a087# CHECK-NEXT: 1 1 0.50 slli a0, a0, 488# CHECK-NEXT: 1 1 0.50 slliw a0, a0, 489# CHECK-NEXT: 1 1 0.50 srl a0, a0, a090# CHECK-NEXT: 1 1 0.50 srlw a0, a0, a091# CHECK-NEXT: 1 3 1.00 mul a0, a0, a092# CHECK-NEXT: 1 3 1.00 mulw a0, a0, a093# CHECK-NEXT: 1 39 39.00 div a0, a0, a094# CHECK-NEXT: 1 39 39.00 divw a0, a0, a095# CHECK-NEXT: 1 5 1.00 * lb a0, 4(a1)96# CHECK-NEXT: 1 5 1.00 * lh a0, 4(a1)97# CHECK-NEXT: 1 3 1.00 * lw a0, 4(a1)98# CHECK-NEXT: 1 3 1.00 * ld a0, 4(a1)99# CHECK-NEXT: 1 3 1.00 * flw fa0, 4(a1)100# CHECK-NEXT: 1 3 1.00 * fld fa0, 4(a1)101# CHECK-NEXT: 1 1 1.00 * sb a0, 4(a1)102# CHECK-NEXT: 1 1 1.00 * sh a0, 4(a1)103# CHECK-NEXT: 1 1 1.00 * sw a0, 4(a1)104# CHECK-NEXT: 1 1 1.00 * sd a0, 4(a1)105# CHECK-NEXT: 1 9 1.00 * * amoswap.w a0, a1, (a0)106# CHECK-NEXT: 1 9 1.00 * * amoswap.d a0, a1, (a0)107# CHECK-NEXT: 1 9 1.00 * lr.w a0, (a0)108# CHECK-NEXT: 1 9 1.00 * lr.d a0, (a0)109# CHECK-NEXT: 1 3 1.00 * sc.w a0, a1, (a0)110# CHECK-NEXT: 1 3 1.00 * sc.d a0, a1, (a0)111# CHECK-NEXT: 1 1 1.00 U csrrw a0, mstatus, zero112# CHECK-NEXT: 1 1 0.50 sh1add a0, a0, a0113# CHECK-NEXT: 1 1 0.50 sh1add.uw a0, a0, a0114# CHECK-NEXT: 1 1 0.50 rori a0, a0, 4115# CHECK-NEXT: 1 1 0.50 roriw a0, a0, 4116# CHECK-NEXT: 1 1 0.50 rol a0, a0, a0117# CHECK-NEXT: 1 1 0.50 rolw a0, a0, a0118# CHECK-NEXT: 1 3 0.50 clz a0, a0119# CHECK-NEXT: 1 3 0.50 clzw a0, a0120# CHECK-NEXT: 1 3 0.50 clmul a0, a0, a0121# CHECK-NEXT: 1 1 0.50 bclri a0, a0, 4122# CHECK-NEXT: 1 1 0.50 bclr a0, a0, a0123# CHECK-NEXT: 1 1 0.50 bexti a0, a0, 4124# CHECK-NEXT: 1 1 0.50 bext a0, a0, a0125 126# CHECK: Resources:127# CHECK-NEXT: [0.0] - Andes45ALU128# CHECK-NEXT: [0.1] - Andes45ALU129# CHECK-NEXT: [1] - Andes45CSR130# CHECK-NEXT: [2] - Andes45FDIV131# CHECK-NEXT: [3] - Andes45FMAC132# CHECK-NEXT: [4] - Andes45FMISC133# CHECK-NEXT: [5] - Andes45FMV134# CHECK-NEXT: [6] - Andes45LSU135# CHECK-NEXT: [7] - Andes45MDU136 137# CHECK: Resource pressure per iteration:138# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7]139# CHECK-NEXT: 10.00 11.00 1.00 - - - - 16.00 80.00140 141# CHECK: Resource pressure by instruction:142# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] Instructions:143# CHECK-NEXT: - 1.00 - - - - - - - add a0, a0, a0144# CHECK-NEXT: 1.00 - - - - - - - - sub a1, a1, a1145# CHECK-NEXT: - 1.00 - - - - - - - addw a0, a0, a0146# CHECK-NEXT: 1.00 - - - - - - - - subw a0, a0, a0147# CHECK-NEXT: - 1.00 - - - - - - - slli a0, a0, 4148# CHECK-NEXT: 1.00 - - - - - - - - slliw a0, a0, 4149# CHECK-NEXT: - 1.00 - - - - - - - srl a0, a0, a0150# CHECK-NEXT: 1.00 - - - - - - - - srlw a0, a0, a0151# CHECK-NEXT: - - - - - - - - 1.00 mul a0, a0, a0152# CHECK-NEXT: - - - - - - - - 1.00 mulw a0, a0, a0153# CHECK-NEXT: - - - - - - - - 39.00 div a0, a0, a0154# CHECK-NEXT: - - - - - - - - 39.00 divw a0, a0, a0155# CHECK-NEXT: - - - - - - - 1.00 - lb a0, 4(a1)156# CHECK-NEXT: - - - - - - - 1.00 - lh a0, 4(a1)157# CHECK-NEXT: - - - - - - - 1.00 - lw a0, 4(a1)158# CHECK-NEXT: - - - - - - - 1.00 - ld a0, 4(a1)159# CHECK-NEXT: - - - - - - - 1.00 - flw fa0, 4(a1)160# CHECK-NEXT: - - - - - - - 1.00 - fld fa0, 4(a1)161# CHECK-NEXT: - - - - - - - 1.00 - sb a0, 4(a1)162# CHECK-NEXT: - - - - - - - 1.00 - sh a0, 4(a1)163# CHECK-NEXT: - - - - - - - 1.00 - sw a0, 4(a1)164# CHECK-NEXT: - - - - - - - 1.00 - sd a0, 4(a1)165# CHECK-NEXT: - - - - - - - 1.00 - amoswap.w a0, a1, (a0)166# CHECK-NEXT: - - - - - - - 1.00 - amoswap.d a0, a1, (a0)167# CHECK-NEXT: - - - - - - - 1.00 - lr.w a0, (a0)168# CHECK-NEXT: - - - - - - - 1.00 - lr.d a0, (a0)169# CHECK-NEXT: - - - - - - - 1.00 - sc.w a0, a1, (a0)170# CHECK-NEXT: - - - - - - - 1.00 - sc.d a0, a1, (a0)171# CHECK-NEXT: - - 1.00 - - - - - - csrrw a0, mstatus, zero172# CHECK-NEXT: - 1.00 - - - - - - - sh1add a0, a0, a0173# CHECK-NEXT: 1.00 - - - - - - - - sh1add.uw a0, a0, a0174# CHECK-NEXT: - 1.00 - - - - - - - rori a0, a0, 4175# CHECK-NEXT: 1.00 - - - - - - - - roriw a0, a0, 4176# CHECK-NEXT: - 1.00 - - - - - - - rol a0, a0, a0177# CHECK-NEXT: 1.00 - - - - - - - - rolw a0, a0, a0178# CHECK-NEXT: - 1.00 - - - - - - - clz a0, a0179# CHECK-NEXT: 1.00 - - - - - - - - clzw a0, a0180# CHECK-NEXT: - 1.00 - - - - - - - clmul a0, a0, a0181# CHECK-NEXT: 1.00 - - - - - - - - bclri a0, a0, 4182# CHECK-NEXT: - 1.00 - - - - - - - bclr a0, a0, a0183# CHECK-NEXT: 1.00 - - - - - - - - bexti a0, a0, 4184# CHECK-NEXT: - 1.00 - - - - - - - bext a0, a0, a0185 186# CHECK: Timeline view:187# CHECK-NEXT: 0123456789 0123456789 012188# CHECK-NEXT: Index 0123456789 0123456789 0123456789189 190# CHECK: [0,0] DE . . . . . . . . . . . add a0, a0, a0191# CHECK-NEXT: [0,1] DE . . . . . . . . . . . sub a1, a1, a1192# CHECK-NEXT: [0,2] .DE . . . . . . . . . . . addw a0, a0, a0193# CHECK-NEXT: [0,3] . DE . . . . . . . . . . . subw a0, a0, a0194# CHECK-NEXT: [0,4] . DE. . . . . . . . . . . slli a0, a0, 4195# CHECK-NEXT: [0,5] . DE . . . . . . . . . . slliw a0, a0, 4196# CHECK-NEXT: [0,6] . DE . . . . . . . . . . srl a0, a0, a0197# CHECK-NEXT: [0,7] . .DE . . . . . . . . . . srlw a0, a0, a0198# CHECK-NEXT: [0,8] . . DeeE . . . . . . . . . mul a0, a0, a0199# CHECK-NEXT: [0,9] . . DeeE . . . . . . . . . mulw a0, a0, a0200# CHECK-NEXT: [0,10] . . . DeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeE div a0, a0, a0201# CHECK-NEXT: Truncated display due to cycle limit202 203# CHECK: Average Wait times (based on the timeline view):204# CHECK-NEXT: [0]: Executions205# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue206# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready207# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage208 209# CHECK: [0] [1] [2] [3]210# CHECK-NEXT: 0. 1 0.0 0.0 0.0 add a0, a0, a0211# CHECK-NEXT: 1. 1 0.0 0.0 0.0 sub a1, a1, a1212# CHECK-NEXT: 2. 1 0.0 0.0 0.0 addw a0, a0, a0213# CHECK-NEXT: 3. 1 0.0 0.0 0.0 subw a0, a0, a0214# CHECK-NEXT: 4. 1 0.0 0.0 0.0 slli a0, a0, 4215# CHECK-NEXT: 5. 1 0.0 0.0 0.0 slliw a0, a0, 4216# CHECK-NEXT: 6. 1 0.0 0.0 0.0 srl a0, a0, a0217# CHECK-NEXT: 7. 1 0.0 0.0 0.0 srlw a0, a0, a0218# CHECK-NEXT: 8. 1 0.0 0.0 0.0 mul a0, a0, a0219# CHECK-NEXT: 9. 1 0.0 0.0 0.0 mulw a0, a0, a0220# CHECK-NEXT: 10. 1 0.0 0.0 0.0 div a0, a0, a0221# CHECK-NEXT: 11. 1 0.0 0.0 0.0 divw a0, a0, a0222# CHECK-NEXT: 12. 1 0.0 0.0 0.0 lb a0, 4(a1)223# CHECK-NEXT: 13. 1 0.0 0.0 0.0 lh a0, 4(a1)224# CHECK-NEXT: 14. 1 0.0 0.0 0.0 lw a0, 4(a1)225# CHECK-NEXT: 15. 1 0.0 0.0 0.0 ld a0, 4(a1)226# CHECK-NEXT: 16. 1 0.0 0.0 0.0 flw fa0, 4(a1)227# CHECK-NEXT: 17. 1 0.0 0.0 0.0 fld fa0, 4(a1)228# CHECK-NEXT: 18. 1 0.0 0.0 0.0 sb a0, 4(a1)229# CHECK-NEXT: 19. 1 0.0 0.0 0.0 sh a0, 4(a1)230# CHECK-NEXT: 20. 1 0.0 0.0 0.0 sw a0, 4(a1)231# CHECK-NEXT: 21. 1 0.0 0.0 0.0 sd a0, 4(a1)232# CHECK-NEXT: 22. 1 0.0 0.0 0.0 amoswap.w a0, a1, (a0)233# CHECK-NEXT: 23. 1 0.0 0.0 0.0 amoswap.d a0, a1, (a0)234# CHECK-NEXT: 24. 1 0.0 0.0 0.0 lr.w a0, (a0)235# CHECK-NEXT: 25. 1 0.0 0.0 0.0 lr.d a0, (a0)236# CHECK-NEXT: 26. 1 0.0 0.0 0.0 sc.w a0, a1, (a0)237# CHECK-NEXT: 27. 1 0.0 0.0 0.0 sc.d a0, a1, (a0)238# CHECK-NEXT: 28. 1 0.0 0.0 0.0 csrrw a0, mstatus, zero239# CHECK-NEXT: 29. 1 0.0 0.0 0.0 sh1add a0, a0, a0240# CHECK-NEXT: 30. 1 0.0 0.0 0.0 sh1add.uw a0, a0, a0241# CHECK-NEXT: 31. 1 0.0 0.0 0.0 rori a0, a0, 4242# CHECK-NEXT: 32. 1 0.0 0.0 0.0 roriw a0, a0, 4243# CHECK-NEXT: 33. 1 0.0 0.0 0.0 rol a0, a0, a0244# CHECK-NEXT: 34. 1 0.0 0.0 0.0 rolw a0, a0, a0245# CHECK-NEXT: 35. 1 0.0 0.0 0.0 clz a0, a0246# CHECK-NEXT: 36. 1 0.0 0.0 0.0 clzw a0, a0247# CHECK-NEXT: 37. 1 0.0 0.0 0.0 clmul a0, a0, a0248# CHECK-NEXT: 38. 1 0.0 0.0 0.0 bclri a0, a0, 4249# CHECK-NEXT: 39. 1 0.0 0.0 0.0 bclr a0, a0, a0250# CHECK-NEXT: 40. 1 0.0 0.0 0.0 bexti a0, a0, 4251# CHECK-NEXT: 41. 1 0.0 0.0 0.0 bext a0, a0, a0252# CHECK-NEXT: 1 0.0 0.0 0.0 <total>253