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1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py2# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -iterations=1 -instruction-tables=full < %s | FileCheck %s3 4vsetvli zero, zero, e32, m1, ta, ma5 6vmslt.vv v0, v4, v207vmsle.vv v8, v4, v208vmsgt.vv v8, v20, v49vmsge.vv v8, v20, v410vmseq.vv v8, v4, v2011vmsne.vv v8, v4, v2012vmsltu.vv v8, v4, v2013vmsleu.vv v8, v4, v2014vmsgtu.vv v8, v20, v415vmsgeu.vv v8, v20, v416 17vmflt.vv v0, v4, v2018vmfle.vv v8, v4, v2019vmfgt.vv v8, v20, v420vmfge.vv v8, v20, v421vmfeq.vv v8, v4, v2022vmfne.vv v8, v4, v2023 24vmadc.vv v8, v4, v2025vmsbc.vv v8, v4, v2026 27vfirst.m a2, v428vpopc.m a2, v429 30viota.m v8, v431 32vmsbf.m v8, v433vmsif.m v8, v434vmsof.m v8, v435 36# CHECK: Resources:37# CHECK-NEXT: [0] - VLEN512SiFive7FDiv:138# CHECK-NEXT: [1] - VLEN512SiFive7IDiv:139# CHECK-NEXT: [2] - VLEN512SiFive7PipeA:140# CHECK-NEXT: [3] - VLEN512SiFive7PipeAB:2 VLEN512SiFive7PipeA, VLEN512SiFive7PipeB41# CHECK-NEXT: [4] - VLEN512SiFive7PipeB:142# CHECK-NEXT: [5] - VLEN512SiFive7VA:143# CHECK-NEXT: [6] - VLEN512SiFive7VCQ:144# CHECK-NEXT: [7] - VLEN512SiFive7VL:145# CHECK-NEXT: [8] - VLEN512SiFive7VS:146 47# CHECK: Instruction Info:48# CHECK-NEXT: [1]: #uOps49# CHECK-NEXT: [2]: Latency50# CHECK-NEXT: [3]: RThroughput51# CHECK-NEXT: [4]: MayLoad52# CHECK-NEXT: [5]: MayStore53# CHECK-NEXT: [6]: HasSideEffects (U)54# CHECK-NEXT: [7]: Bypass Latency55# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])56# CHECK-NEXT: [9]: LLVM Opcode Name57 58# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:59# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m1, ta, ma60# CHECK-NEXT: 1 5 2.00 5 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMSLT_VV vmslt.vv v0, v4, v2061# CHECK-NEXT: 1 5 2.00 5 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMSLE_VV vmsle.vv v8, v4, v2062# CHECK-NEXT: 1 5 2.00 5 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMSLT_VV vmslt.vv v8, v4, v2063# CHECK-NEXT: 1 5 2.00 5 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMSLE_VV vmsle.vv v8, v4, v2064# CHECK-NEXT: 1 5 2.00 5 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMSEQ_VV vmseq.vv v8, v4, v2065# CHECK-NEXT: 1 5 2.00 5 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMSNE_VV vmsne.vv v8, v4, v2066# CHECK-NEXT: 1 5 2.00 5 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMSLTU_VV vmsltu.vv v8, v4, v2067# CHECK-NEXT: 1 5 2.00 5 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMSLEU_VV vmsleu.vv v8, v4, v2068# CHECK-NEXT: 1 5 2.00 5 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMSLTU_VV vmsltu.vv v8, v4, v2069# CHECK-NEXT: 1 5 2.00 5 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMSLEU_VV vmsleu.vv v8, v4, v2070# CHECK-NEXT: 1 5 2.00 5 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMFLT_VV vmflt.vv v0, v4, v2071# CHECK-NEXT: 1 5 2.00 5 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMFLE_VV vmfle.vv v8, v4, v2072# CHECK-NEXT: 1 5 2.00 5 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMFLT_VV vmflt.vv v8, v4, v2073# CHECK-NEXT: 1 5 2.00 5 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMFLE_VV vmfle.vv v8, v4, v2074# CHECK-NEXT: 1 5 2.00 5 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMFEQ_VV vmfeq.vv v8, v4, v2075# CHECK-NEXT: 1 5 2.00 5 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMFNE_VV vmfne.vv v8, v4, v2076# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMADC_VV vmadc.vv v8, v4, v2077# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMSBC_VV vmsbc.vv v8, v4, v2078# CHECK-NEXT: 1 11 3.00 11 VLEN512SiFive7VA[1,4],VLEN512SiFive7VCQ VFIRST_M vfirst.m a2, v479# CHECK-NEXT: 1 11 3.00 11 VLEN512SiFive7VA[1,4],VLEN512SiFive7VCQ VCPOP_M vcpop.m a2, v480# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VIOTA_M viota.m v8, v481# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VMSBF_M vmsbf.m v8, v482# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VMSIF_M vmsif.m v8, v483# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VMSOF_M vmsof.m v8, v484 85# CHECK: Resources:86# CHECK-NEXT: [0] - VLEN512SiFive7FDiv87# CHECK-NEXT: [1] - VLEN512SiFive7IDiv88# CHECK-NEXT: [2] - VLEN512SiFive7PipeA89# CHECK-NEXT: [3] - VLEN512SiFive7PipeB90# CHECK-NEXT: [4] - VLEN512SiFive7VA91# CHECK-NEXT: [5] - VLEN512SiFive7VCQ92# CHECK-NEXT: [6] - VLEN512SiFive7VL93# CHECK-NEXT: [7] - VLEN512SiFive7VS94 95# CHECK: Resource pressure per iteration:96# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]97# CHECK-NEXT: - - 1.00 - 71.00 24.00 - -98 99# CHECK: Resource pressure by instruction:100# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:101# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, ta, ma102# CHECK-NEXT: - - - - 3.00 1.00 - - vmslt.vv v0, v4, v20103# CHECK-NEXT: - - - - 3.00 1.00 - - vmsle.vv v8, v4, v20104# CHECK-NEXT: - - - - 3.00 1.00 - - vmslt.vv v8, v4, v20105# CHECK-NEXT: - - - - 3.00 1.00 - - vmsle.vv v8, v4, v20106# CHECK-NEXT: - - - - 3.00 1.00 - - vmseq.vv v8, v4, v20107# CHECK-NEXT: - - - - 3.00 1.00 - - vmsne.vv v8, v4, v20108# CHECK-NEXT: - - - - 3.00 1.00 - - vmsltu.vv v8, v4, v20109# CHECK-NEXT: - - - - 3.00 1.00 - - vmsleu.vv v8, v4, v20110# CHECK-NEXT: - - - - 3.00 1.00 - - vmsltu.vv v8, v4, v20111# CHECK-NEXT: - - - - 3.00 1.00 - - vmsleu.vv v8, v4, v20112# CHECK-NEXT: - - - - 3.00 1.00 - - vmflt.vv v0, v4, v20113# CHECK-NEXT: - - - - 3.00 1.00 - - vmfle.vv v8, v4, v20114# CHECK-NEXT: - - - - 3.00 1.00 - - vmflt.vv v8, v4, v20115# CHECK-NEXT: - - - - 3.00 1.00 - - vmfle.vv v8, v4, v20116# CHECK-NEXT: - - - - 3.00 1.00 - - vmfeq.vv v8, v4, v20117# CHECK-NEXT: - - - - 3.00 1.00 - - vmfne.vv v8, v4, v20118# CHECK-NEXT: - - - - 3.00 1.00 - - vmadc.vv v8, v4, v20119# CHECK-NEXT: - - - - 3.00 1.00 - - vmsbc.vv v8, v4, v20120# CHECK-NEXT: - - - - 4.00 1.00 - - vfirst.m a2, v4121# CHECK-NEXT: - - - - 4.00 1.00 - - vcpop.m a2, v4122# CHECK-NEXT: - - - - 3.00 1.00 - - viota.m v8, v4123# CHECK-NEXT: - - - - 2.00 1.00 - - vmsbf.m v8, v4124# CHECK-NEXT: - - - - 2.00 1.00 - - vmsif.m v8, v4125# CHECK-NEXT: - - - - 2.00 1.00 - - vmsof.m v8, v4126