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1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py2# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -instruction-tables=full -iterations=1 < %s \3# RUN: | FileCheck %s4 5lh t0, 0(sp)6flh fa0, 0(sp)7lw t2, 0(sp)8flw fa2, 0(sp)9ld t4, 0(sp)10fld fa4, 0(sp)11 12sh t1, 0(sp)13fsh fa1, 0(sp)14sw t3, 0(sp)15fsw fa3, 0(sp)16sd t5, 0(sp)17fsd fa5, 0(sp)18 19# CHECK: Resources:20# CHECK-NEXT: [0] - VLEN512SiFive7FDiv:121# CHECK-NEXT: [1] - VLEN512SiFive7IDiv:122# CHECK-NEXT: [2] - VLEN512SiFive7PipeA:123# CHECK-NEXT: [3] - VLEN512SiFive7PipeAB:2 VLEN512SiFive7PipeA, VLEN512SiFive7PipeB24# CHECK-NEXT: [4] - VLEN512SiFive7PipeB:125# CHECK-NEXT: [5] - VLEN512SiFive7VA:126# CHECK-NEXT: [6] - VLEN512SiFive7VCQ:127# CHECK-NEXT: [7] - VLEN512SiFive7VL:128# CHECK-NEXT: [8] - VLEN512SiFive7VS:129 30# CHECK: Instruction Info:31# CHECK-NEXT: [1]: #uOps32# CHECK-NEXT: [2]: Latency33# CHECK-NEXT: [3]: RThroughput34# CHECK-NEXT: [4]: MayLoad35# CHECK-NEXT: [5]: MayStore36# CHECK-NEXT: [6]: HasSideEffects (U)37# CHECK-NEXT: [7]: Bypass Latency38# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])39# CHECK-NEXT: [9]: LLVM Opcode Name40 41# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:42# CHECK-NEXT: 1 3 1.00 * 3 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB LH lh t0, 0(sp)43# CHECK-NEXT: 1 3 1.00 * 3 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB FLH flh fa0, 0(sp)44# CHECK-NEXT: 1 3 1.00 * 3 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB C_LWSP lw t2, 0(sp)45# CHECK-NEXT: 1 3 1.00 * 3 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB FLW flw fa2, 0(sp)46# CHECK-NEXT: 1 3 1.00 * 3 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB C_LDSP ld t4, 0(sp)47# CHECK-NEXT: 1 3 1.00 * 3 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB C_FLDSP fld fa4, 0(sp)48# CHECK-NEXT: 1 1 1.00 * 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB SH sh t1, 0(sp)49# CHECK-NEXT: 1 1 1.00 * 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB FSH fsh fa1, 0(sp)50# CHECK-NEXT: 1 1 1.00 * 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB C_SWSP sw t3, 0(sp)51# CHECK-NEXT: 1 1 1.00 * 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB FSW fsw fa3, 0(sp)52# CHECK-NEXT: 1 1 1.00 * 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB C_SDSP sd t5, 0(sp)53# CHECK-NEXT: 1 1 1.00 * 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB C_FSDSP fsd fa5, 0(sp)54 55# CHECK: Resources:56# CHECK-NEXT: [0] - VLEN512SiFive7FDiv57# CHECK-NEXT: [1] - VLEN512SiFive7IDiv58# CHECK-NEXT: [2] - VLEN512SiFive7PipeA59# CHECK-NEXT: [3] - VLEN512SiFive7PipeB60# CHECK-NEXT: [4] - VLEN512SiFive7VA61# CHECK-NEXT: [5] - VLEN512SiFive7VCQ62# CHECK-NEXT: [6] - VLEN512SiFive7VL63# CHECK-NEXT: [7] - VLEN512SiFive7VS64 65# CHECK: Resource pressure per iteration:66# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]67# CHECK-NEXT: - - 12.00 - - - - -68 69# CHECK: Resource pressure by instruction:70# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:71# CHECK-NEXT: - - 1.00 - - - - - lh t0, 0(sp)72# CHECK-NEXT: - - 1.00 - - - - - flh fa0, 0(sp)73# CHECK-NEXT: - - 1.00 - - - - - lw t2, 0(sp)74# CHECK-NEXT: - - 1.00 - - - - - flw fa2, 0(sp)75# CHECK-NEXT: - - 1.00 - - - - - ld t4, 0(sp)76# CHECK-NEXT: - - 1.00 - - - - - fld fa4, 0(sp)77# CHECK-NEXT: - - 1.00 - - - - - sh t1, 0(sp)78# CHECK-NEXT: - - 1.00 - - - - - fsh fa1, 0(sp)79# CHECK-NEXT: - - 1.00 - - - - - sw t3, 0(sp)80# CHECK-NEXT: - - 1.00 - - - - - fsw fa3, 0(sp)81# CHECK-NEXT: - - 1.00 - - - - - sd t5, 0(sp)82# CHECK-NEXT: - - 1.00 - - - - - fsd fa5, 0(sp)83