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1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py2# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -mattr='+xsfvfnrclipxfqf' -iterations=1 -instruction-tables=full %s | \3# RUN: FileCheck %s4 5vsetvli a0, zero, e8, mf8, ta, ma6sf.vfnrclip.xu.f.qf v4, v8, fa27 8vsetvli a0, zero, e8, mf4, ta, ma9sf.vfnrclip.xu.f.qf v4, v8, fa210 11vsetvli a0, zero, e8, mf2, ta, ma12sf.vfnrclip.xu.f.qf v4, v8, fa213 14vsetvli a0, zero, e8, m1, ta, ma15sf.vfnrclip.xu.f.qf v4, v8, fa216 17vsetvli a0, zero, e8, m2, ta, ma18sf.vfnrclip.xu.f.qf v4, v8, fa219 20# CHECK: Resources:21# CHECK-NEXT: [0] - VLEN512SiFive7FDiv:122# CHECK-NEXT: [1] - VLEN512SiFive7IDiv:123# CHECK-NEXT: [2] - VLEN512SiFive7PipeA:124# CHECK-NEXT: [3] - VLEN512SiFive7PipeAB:2 VLEN512SiFive7PipeA, VLEN512SiFive7PipeB25# CHECK-NEXT: [4] - VLEN512SiFive7PipeB:126# CHECK-NEXT: [5] - VLEN512SiFive7VA:127# CHECK-NEXT: [6] - VLEN512SiFive7VCQ:128# CHECK-NEXT: [7] - VLEN512SiFive7VL:129# CHECK-NEXT: [8] - VLEN512SiFive7VS:130 31# CHECK: Instruction Info:32# CHECK-NEXT: [1]: #uOps33# CHECK-NEXT: [2]: Latency34# CHECK-NEXT: [3]: RThroughput35# CHECK-NEXT: [4]: MayLoad36# CHECK-NEXT: [5]: MayStore37# CHECK-NEXT: [6]: HasSideEffects (U)38# CHECK-NEXT: [7]: Bypass Latency39# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])40# CHECK-NEXT: [9]: LLVM Opcode Name41 42# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:43# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli a0, zero, e8, mf8, ta, ma44# CHECK-NEXT: 1 7 1.00 7 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ SF_VFNRCLIP_XU_F_QF sf.vfnrclip.xu.f.qf v4, v8, fa245# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli a0, zero, e8, mf4, ta, ma46# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ SF_VFNRCLIP_XU_F_QF sf.vfnrclip.xu.f.qf v4, v8, fa247# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli a0, zero, e8, mf2, ta, ma48# CHECK-NEXT: 1 10 4.00 10 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ SF_VFNRCLIP_XU_F_QF sf.vfnrclip.xu.f.qf v4, v8, fa249# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli a0, zero, e8, m1, ta, ma50# CHECK-NEXT: 1 13 8.00 13 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ SF_VFNRCLIP_XU_F_QF sf.vfnrclip.xu.f.qf v4, v8, fa251# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli a0, zero, e8, m2, ta, ma52# CHECK-NEXT: 1 19 16.00 19 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ SF_VFNRCLIP_XU_F_QF sf.vfnrclip.xu.f.qf v4, v8, fa253 54# CHECK: Resources:55# CHECK-NEXT: [0] - VLEN512SiFive7FDiv56# CHECK-NEXT: [1] - VLEN512SiFive7IDiv57# CHECK-NEXT: [2] - VLEN512SiFive7PipeA58# CHECK-NEXT: [3] - VLEN512SiFive7PipeB59# CHECK-NEXT: [4] - VLEN512SiFive7VA60# CHECK-NEXT: [5] - VLEN512SiFive7VCQ61# CHECK-NEXT: [6] - VLEN512SiFive7VL62# CHECK-NEXT: [7] - VLEN512SiFive7VS63 64# CHECK: Resource pressure per iteration:65# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]66# CHECK-NEXT: - - 5.00 - 36.00 5.00 - -67 68# CHECK: Resource pressure by instruction:69# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:70# CHECK-NEXT: - - 1.00 - - - - - vsetvli a0, zero, e8, mf8, ta, ma71# CHECK-NEXT: - - - - 2.00 1.00 - - sf.vfnrclip.xu.f.qf v4, v8, fa272# CHECK-NEXT: - - 1.00 - - - - - vsetvli a0, zero, e8, mf4, ta, ma73# CHECK-NEXT: - - - - 3.00 1.00 - - sf.vfnrclip.xu.f.qf v4, v8, fa274# CHECK-NEXT: - - 1.00 - - - - - vsetvli a0, zero, e8, mf2, ta, ma75# CHECK-NEXT: - - - - 5.00 1.00 - - sf.vfnrclip.xu.f.qf v4, v8, fa276# CHECK-NEXT: - - 1.00 - - - - - vsetvli a0, zero, e8, m1, ta, ma77# CHECK-NEXT: - - - - 9.00 1.00 - - sf.vfnrclip.xu.f.qf v4, v8, fa278# CHECK-NEXT: - - 1.00 - - - - - vsetvli a0, zero, e8, m2, ta, ma79# CHECK-NEXT: - - - - 17.00 1.00 - - sf.vfnrclip.xu.f.qf v4, v8, fa280