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1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py2# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -mattr='+xsfvfwmaccqqq' -instruction-tables=full -iterations=1 %s | \3# RUN: FileCheck %s4 5vsetvli zero, zero, e16, mf4, ta, ma6sf.vfwmacc.4x4x4 v16, v0, v87vsetvli zero, zero, e16, mf2, ta, ma8sf.vfwmacc.4x4x4 v16, v0, v89vsetvli zero, zero, e16, m1, ta, ma10sf.vfwmacc.4x4x4 v16, v0, v811vsetvli zero, zero, e16, m2, ta, ma12sf.vfwmacc.4x4x4 v16, v0, v813vsetvli zero, zero, e16, m4, ta, ma14sf.vfwmacc.4x4x4 v16, v0, v815 16# CHECK: Resources:17# CHECK-NEXT: [0] - VLEN512SiFive7FDiv:118# CHECK-NEXT: [1] - VLEN512SiFive7IDiv:119# CHECK-NEXT: [2] - VLEN512SiFive7PipeA:120# CHECK-NEXT: [3] - VLEN512SiFive7PipeAB:2 VLEN512SiFive7PipeA, VLEN512SiFive7PipeB21# CHECK-NEXT: [4] - VLEN512SiFive7PipeB:122# CHECK-NEXT: [5] - VLEN512SiFive7VA:123# CHECK-NEXT: [6] - VLEN512SiFive7VCQ:124# CHECK-NEXT: [7] - VLEN512SiFive7VL:125# CHECK-NEXT: [8] - VLEN512SiFive7VS:126 27# CHECK: Instruction Info:28# CHECK-NEXT: [1]: #uOps29# CHECK-NEXT: [2]: Latency30# CHECK-NEXT: [3]: RThroughput31# CHECK-NEXT: [4]: MayLoad32# CHECK-NEXT: [5]: MayStore33# CHECK-NEXT: [6]: HasSideEffects (U)34# CHECK-NEXT: [7]: Bypass Latency35# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])36# CHECK-NEXT: [9]: LLVM Opcode Name37 38# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:39# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, mf4, ta, ma40# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ SF_VFWMACC_4x4x4 sf.vfwmacc.4x4x4 v16, v0, v841# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, mf2, ta, ma42# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ SF_VFWMACC_4x4x4 sf.vfwmacc.4x4x4 v16, v0, v843# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m1, ta, ma44# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ SF_VFWMACC_4x4x4 sf.vfwmacc.4x4x4 v16, v0, v845# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m2, ta, ma46# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ SF_VFWMACC_4x4x4 sf.vfwmacc.4x4x4 v16, v0, v847# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m4, ta, ma48# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ SF_VFWMACC_4x4x4 sf.vfwmacc.4x4x4 v16, v0, v849 50# CHECK: Resources:51# CHECK-NEXT: [0] - VLEN512SiFive7FDiv52# CHECK-NEXT: [1] - VLEN512SiFive7IDiv53# CHECK-NEXT: [2] - VLEN512SiFive7PipeA54# CHECK-NEXT: [3] - VLEN512SiFive7PipeB55# CHECK-NEXT: [4] - VLEN512SiFive7VA56# CHECK-NEXT: [5] - VLEN512SiFive7VCQ57# CHECK-NEXT: [6] - VLEN512SiFive7VL58# CHECK-NEXT: [7] - VLEN512SiFive7VS59 60# CHECK: Resource pressure per iteration:61# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]62# CHECK-NEXT: - - 5.00 - 21.00 5.00 - -63 64# CHECK: Resource pressure by instruction:65# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:66# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, ta, ma67# CHECK-NEXT: - - - - 2.00 1.00 - - sf.vfwmacc.4x4x4 v16, v0, v868# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, ta, ma69# CHECK-NEXT: - - - - 2.00 1.00 - - sf.vfwmacc.4x4x4 v16, v0, v870# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, ta, ma71# CHECK-NEXT: - - - - 3.00 1.00 - - sf.vfwmacc.4x4x4 v16, v0, v872# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, ta, ma73# CHECK-NEXT: - - - - 5.00 1.00 - - sf.vfwmacc.4x4x4 v16, v0, v874# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, ta, ma75# CHECK-NEXT: - - - - 9.00 1.00 - - sf.vfwmacc.4x4x4 v16, v0, v876