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1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py2# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -mattr='+xsfvqmaccqoq,+xsfvqmaccdod' -instruction-tables=full -iterations=1 %s | \3# RUN: FileCheck %s4 5vsetvli zero, zero, e8, m1, ta, ma6sf.vqmacc.2x8x2 v16, v0, v87vsetvli zero, zero, e8, m2, ta, ma8sf.vqmacc.2x8x2 v16, v0, v89vsetvli zero, zero, e8, m4, ta, ma10sf.vqmacc.2x8x2 v16, v0, v811vsetvli zero, zero, e8, m8, ta, ma12sf.vqmacc.2x8x2 v16, v0, v813 14vsetvli zero, zero, e8, mf2, ta, ma15sf.vqmacc.4x8x4 v16, v0, v816vsetvli zero, zero, e8, m1, ta, ma17sf.vqmacc.4x8x4 v16, v0, v818vsetvli zero, zero, e8, m2, ta, ma19sf.vqmacc.4x8x4 v16, v0, v820vsetvli zero, zero, e8, m4, ta, ma21sf.vqmacc.4x8x4 v16, v0, v822 23# CHECK: Resources:24# CHECK-NEXT: [0] - VLEN512SiFive7FDiv:125# CHECK-NEXT: [1] - VLEN512SiFive7IDiv:126# CHECK-NEXT: [2] - VLEN512SiFive7PipeA:127# CHECK-NEXT: [3] - VLEN512SiFive7PipeAB:2 VLEN512SiFive7PipeA, VLEN512SiFive7PipeB28# CHECK-NEXT: [4] - VLEN512SiFive7PipeB:129# CHECK-NEXT: [5] - VLEN512SiFive7VA:130# CHECK-NEXT: [6] - VLEN512SiFive7VCQ:131# CHECK-NEXT: [7] - VLEN512SiFive7VL:132# CHECK-NEXT: [8] - VLEN512SiFive7VS:133 34# CHECK: Instruction Info:35# CHECK-NEXT: [1]: #uOps36# CHECK-NEXT: [2]: Latency37# CHECK-NEXT: [3]: RThroughput38# CHECK-NEXT: [4]: MayLoad39# CHECK-NEXT: [5]: MayStore40# CHECK-NEXT: [6]: HasSideEffects (U)41# CHECK-NEXT: [7]: Bypass Latency42# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])43# CHECK-NEXT: [9]: LLVM Opcode Name44 45# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:46# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, m1, ta, ma47# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ SF_VQMACC_2x8x2 sf.vqmacc.2x8x2 v16, v0, v848# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, m2, ta, ma49# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ SF_VQMACC_2x8x2 sf.vqmacc.2x8x2 v16, v0, v850# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, m4, ta, ma51# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ SF_VQMACC_2x8x2 sf.vqmacc.2x8x2 v16, v0, v852# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, m8, ta, ma53# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ SF_VQMACC_2x8x2 sf.vqmacc.2x8x2 v16, v0, v854# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, mf2, ta, ma55# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ SF_VQMACC_4x8x4 sf.vqmacc.4x8x4 v16, v0, v856# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, m1, ta, ma57# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ SF_VQMACC_4x8x4 sf.vqmacc.4x8x4 v16, v0, v858# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, m2, ta, ma59# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ SF_VQMACC_4x8x4 sf.vqmacc.4x8x4 v16, v0, v860# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, m4, ta, ma61# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ SF_VQMACC_4x8x4 sf.vqmacc.4x8x4 v16, v0, v862 63# CHECK: Resources:64# CHECK-NEXT: [0] - VLEN512SiFive7FDiv65# CHECK-NEXT: [1] - VLEN512SiFive7IDiv66# CHECK-NEXT: [2] - VLEN512SiFive7PipeA67# CHECK-NEXT: [3] - VLEN512SiFive7PipeB68# CHECK-NEXT: [4] - VLEN512SiFive7VA69# CHECK-NEXT: [5] - VLEN512SiFive7VCQ70# CHECK-NEXT: [6] - VLEN512SiFive7VL71# CHECK-NEXT: [7] - VLEN512SiFive7VS72 73# CHECK: Resource pressure per iteration:74# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]75# CHECK-NEXT: - - 8.00 - 53.00 8.00 - -76 77# CHECK: Resource pressure by instruction:78# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:79# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m1, ta, ma80# CHECK-NEXT: - - - - 3.00 1.00 - - sf.vqmacc.2x8x2 v16, v0, v881# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m2, ta, ma82# CHECK-NEXT: - - - - 5.00 1.00 - - sf.vqmacc.2x8x2 v16, v0, v883# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m4, ta, ma84# CHECK-NEXT: - - - - 9.00 1.00 - - sf.vqmacc.2x8x2 v16, v0, v885# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m8, ta, ma86# CHECK-NEXT: - - - - 17.00 1.00 - - sf.vqmacc.2x8x2 v16, v0, v887# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf2, ta, ma88# CHECK-NEXT: - - - - 2.00 1.00 - - sf.vqmacc.4x8x4 v16, v0, v889# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m1, ta, ma90# CHECK-NEXT: - - - - 3.00 1.00 - - sf.vqmacc.4x8x4 v16, v0, v891# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m2, ta, ma92# CHECK-NEXT: - - - - 5.00 1.00 - - sf.vqmacc.4x8x4 v16, v0, v893# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m4, ta, ma94# CHECK-NEXT: - - - - 9.00 1.00 - - sf.vqmacc.4x8x4 v16, v0, v895