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1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py2# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 < %s | FileCheck %s3 4mul s6, s6, s75 6mulw s4, s4, a27 8cpop t1, t19 10cpopw t2, t211 12# CHECK: Iterations: 113# CHECK-NEXT: Instructions: 414# CHECK-NEXT: Total Cycles: 815# CHECK-NEXT: Total uOps: 416 17# CHECK: Dispatch Width: 318# CHECK-NEXT: uOps Per Cycle: 0.5019# CHECK-NEXT: IPC: 0.5020# CHECK-NEXT: Block RThroughput: 4.021 22# CHECK: Instruction Info:23# CHECK-NEXT: [1]: #uOps24# CHECK-NEXT: [2]: Latency25# CHECK-NEXT: [3]: RThroughput26# CHECK-NEXT: [4]: MayLoad27# CHECK-NEXT: [5]: MayStore28# CHECK-NEXT: [6]: HasSideEffects (U)29 30# CHECK: [1] [2] [3] [4] [5] [6] Instructions:31# CHECK-NEXT: 1 2 1.00 mul s6, s6, s732# CHECK-NEXT: 1 2 1.00 mulw s4, s4, a233# CHECK-NEXT: 1 2 1.00 cpop t1, t134# CHECK-NEXT: 1 2 1.00 cpopw t2, t235 36# CHECK: Resources:37# CHECK-NEXT: [0] - SiFiveP400Div38# CHECK-NEXT: [1] - SiFiveP400FEXQ039# CHECK-NEXT: [2] - SiFiveP400FloatDiv40# CHECK-NEXT: [3] - SiFiveP400IEXQ041# CHECK-NEXT: [4] - SiFiveP400IEXQ142# CHECK-NEXT: [5] - SiFiveP400IEXQ243# CHECK-NEXT: [6] - SiFiveP400Load44# CHECK-NEXT: [7] - SiFiveP400Store45# CHECK-NEXT: [8] - SiFiveP400VDiv46# CHECK-NEXT: [9] - SiFiveP400VEXQ047# CHECK-NEXT: [10] - SiFiveP400VFloatDiv48# CHECK-NEXT: [11] - SiFiveP400VLD49# CHECK-NEXT: [12] - SiFiveP400VST50 51# CHECK: Resource pressure per iteration:52# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]53# CHECK-NEXT: - - - - - 4.00 - - - - - - -54 55# CHECK: Resource pressure by instruction:56# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:57# CHECK-NEXT: - - - - - 1.00 - - - - - - - mul s6, s6, s758# CHECK-NEXT: - - - - - 1.00 - - - - - - - mulw s4, s4, a259# CHECK-NEXT: - - - - - 1.00 - - - - - - - cpop t1, t160# CHECK-NEXT: - - - - - 1.00 - - - - - - - cpopw t2, t261