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1 2# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py3# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 < %s | FileCheck %s4 5vsetvli zero, zero, e32, m1, ta, ma6 7vsll.vv v1, v2, v58vsll.vx v1, v2, t09vsll.vi v1, v2, 710 11vsrl.vv v1, v2, v512vsrl.vx v1, v2, t013vsrl.vi v1, v2, 714 15vsra.vv v1, v2, v516vsra.vx v1, v2, t017vsra.vi v1, v2, 718 19vsetvli zero, zero, e32, mf4, ta, ma20 21vsll.vv v1, v2, v522vsll.vx v1, v2, t023vsll.vi v1, v2, 724 25vsrl.vv v1, v2, v526vsrl.vx v1, v2, t027vsrl.vi v1, v2, 728 29vsra.vv v1, v2, v530vsra.vx v1, v2, t031vsra.vi v1, v2, 732 33vsetvli zero, zero, e32, m8, ta, ma34 35vmul.vv v1, v2, v536vmul.vx v1, v2, t137 38vmadd.vv v1, v2, v539vmadd.vx v1, t1, v240 41# CHECK: Iterations: 142# CHECK-NEXT: Instructions: 2543# CHECK-NEXT: Total Cycles: 5744# CHECK-NEXT: Total uOps: 2545 46# CHECK: Dispatch Width: 347# CHECK-NEXT: uOps Per Cycle: 0.4448# CHECK-NEXT: IPC: 0.4449# CHECK-NEXT: Block RThroughput: 50.050 51# CHECK: Instruction Info:52# CHECK-NEXT: [1]: #uOps53# CHECK-NEXT: [2]: Latency54# CHECK-NEXT: [3]: RThroughput55# CHECK-NEXT: [4]: MayLoad56# CHECK-NEXT: [5]: MayStore57# CHECK-NEXT: [6]: HasSideEffects (U)58 59# CHECK: [1] [2] [3] [4] [5] [6] Instructions:60# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma61# CHECK-NEXT: 1 2 1.00 vsll.vv v1, v2, v562# CHECK-NEXT: 1 2 1.00 vsll.vx v1, v2, t063# CHECK-NEXT: 1 2 1.00 vsll.vi v1, v2, 764# CHECK-NEXT: 1 2 1.00 vsrl.vv v1, v2, v565# CHECK-NEXT: 1 2 1.00 vsrl.vx v1, v2, t066# CHECK-NEXT: 1 2 1.00 vsrl.vi v1, v2, 767# CHECK-NEXT: 1 2 1.00 vsra.vv v1, v2, v568# CHECK-NEXT: 1 2 1.00 vsra.vx v1, v2, t069# CHECK-NEXT: 1 2 1.00 vsra.vi v1, v2, 770# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, ta, ma71# CHECK-NEXT: 1 2 1.00 vsll.vv v1, v2, v572# CHECK-NEXT: 1 2 1.00 vsll.vx v1, v2, t073# CHECK-NEXT: 1 2 1.00 vsll.vi v1, v2, 774# CHECK-NEXT: 1 2 1.00 vsrl.vv v1, v2, v575# CHECK-NEXT: 1 2 1.00 vsrl.vx v1, v2, t076# CHECK-NEXT: 1 2 1.00 vsrl.vi v1, v2, 777# CHECK-NEXT: 1 2 1.00 vsra.vv v1, v2, v578# CHECK-NEXT: 1 2 1.00 vsra.vx v1, v2, t079# CHECK-NEXT: 1 2 1.00 vsra.vi v1, v2, 780# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma81# CHECK-NEXT: 1 9 8.00 vmul.vv v1, v2, v582# CHECK-NEXT: 1 9 8.00 vmul.vx v1, v2, t183# CHECK-NEXT: 1 9 8.00 vmadd.vv v1, v2, v584# CHECK-NEXT: 1 9 8.00 vmadd.vx v1, t1, v285 86# CHECK: Resources:87# CHECK-NEXT: [0] - SiFiveP400Div88# CHECK-NEXT: [1] - SiFiveP400FEXQ089# CHECK-NEXT: [2] - SiFiveP400FloatDiv90# CHECK-NEXT: [3] - SiFiveP400IEXQ091# CHECK-NEXT: [4] - SiFiveP400IEXQ192# CHECK-NEXT: [5] - SiFiveP400IEXQ293# CHECK-NEXT: [6] - SiFiveP400Load94# CHECK-NEXT: [7] - SiFiveP400Store95# CHECK-NEXT: [8] - SiFiveP400VDiv96# CHECK-NEXT: [9] - SiFiveP400VEXQ097# CHECK-NEXT: [10] - SiFiveP400VFloatDiv98# CHECK-NEXT: [11] - SiFiveP400VLD99# CHECK-NEXT: [12] - SiFiveP400VST100 101# CHECK: Resource pressure per iteration:102# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]103# CHECK-NEXT: - - - - 3.00 - - - - 50.00 - - -104 105# CHECK: Resource pressure by instruction:106# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:107# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma108# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsll.vv v1, v2, v5109# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsll.vx v1, v2, t0110# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsll.vi v1, v2, 7111# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsrl.vv v1, v2, v5112# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsrl.vx v1, v2, t0113# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsrl.vi v1, v2, 7114# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsra.vv v1, v2, v5115# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsra.vx v1, v2, t0116# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsra.vi v1, v2, 7117# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf4, ta, ma118# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsll.vv v1, v2, v5119# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsll.vx v1, v2, t0120# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsll.vi v1, v2, 7121# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsrl.vv v1, v2, v5122# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsrl.vx v1, v2, t0123# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsrl.vi v1, v2, 7124# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsra.vv v1, v2, v5125# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsra.vx v1, v2, t0126# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsra.vi v1, v2, 7127# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma128# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmul.vv v1, v2, v5129# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmul.vx v1, v2, t1130# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmadd.vv v1, v2, v5131# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmadd.vx v1, t1, v2132 133