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1 2# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py3# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 < %s | FileCheck %s4 5# These instructions only work with e646 7vsetvli zero, zero, e64, m1, tu, mu8vclmul.vv v4, v8, v129vclmul.vx v4, v8, a010vclmulh.vv v4, v8, v1211vclmulh.vx v4, v8, a012 13vsetvli zero, zero, e64, m2, tu, mu14vclmul.vv v4, v8, v1215vclmul.vx v4, v8, a016vclmulh.vv v4, v8, v1217vclmulh.vx v4, v8, a018 19vsetvli zero, zero, e64, m4, tu, mu20vclmul.vv v4, v8, v1221vclmul.vx v4, v8, a022vclmulh.vv v4, v8, v1223vclmulh.vx v4, v8, a024 25vsetvli zero, zero, e64, m8, tu, mu26vclmul.vv v8, v12, v2427vclmul.vx v8, v12, a028vclmulh.vv v8, v12, v2429vclmulh.vx v8, v12, a030 31# CHECK: Iterations: 132# CHECK-NEXT: Instructions: 2033# CHECK-NEXT: Total Cycles: 5834# CHECK-NEXT: Total uOps: 2035 36# CHECK: Dispatch Width: 337# CHECK-NEXT: uOps Per Cycle: 0.3438# CHECK-NEXT: IPC: 0.3439# CHECK-NEXT: Block RThroughput: 60.040 41# CHECK: Instruction Info:42# CHECK-NEXT: [1]: #uOps43# CHECK-NEXT: [2]: Latency44# CHECK-NEXT: [3]: RThroughput45# CHECK-NEXT: [4]: MayLoad46# CHECK-NEXT: [5]: MayStore47# CHECK-NEXT: [6]: HasSideEffects (U)48 49# CHECK: [1] [2] [3] [4] [5] [6] Instructions:50# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu51# CHECK-NEXT: 1 2 1.00 vclmul.vv v4, v8, v1252# CHECK-NEXT: 1 2 1.00 vclmul.vx v4, v8, a053# CHECK-NEXT: 1 2 1.00 vclmulh.vv v4, v8, v1254# CHECK-NEXT: 1 2 1.00 vclmulh.vx v4, v8, a055# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu56# CHECK-NEXT: 1 2 2.00 vclmul.vv v4, v8, v1257# CHECK-NEXT: 1 2 2.00 vclmul.vx v4, v8, a058# CHECK-NEXT: 1 2 2.00 vclmulh.vv v4, v8, v1259# CHECK-NEXT: 1 2 2.00 vclmulh.vx v4, v8, a060# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu61# CHECK-NEXT: 1 2 4.00 vclmul.vv v4, v8, v1262# CHECK-NEXT: 1 2 4.00 vclmul.vx v4, v8, a063# CHECK-NEXT: 1 2 4.00 vclmulh.vv v4, v8, v1264# CHECK-NEXT: 1 2 4.00 vclmulh.vx v4, v8, a065# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu66# CHECK-NEXT: 1 2 8.00 vclmul.vv v8, v12, v2467# CHECK-NEXT: 1 2 8.00 vclmul.vx v8, v12, a068# CHECK-NEXT: 1 2 8.00 vclmulh.vv v8, v12, v2469# CHECK-NEXT: 1 2 8.00 vclmulh.vx v8, v12, a070 71# CHECK: Resources:72# CHECK-NEXT: [0] - SiFiveP400Div73# CHECK-NEXT: [1] - SiFiveP400FEXQ074# CHECK-NEXT: [2] - SiFiveP400FloatDiv75# CHECK-NEXT: [3] - SiFiveP400IEXQ076# CHECK-NEXT: [4] - SiFiveP400IEXQ177# CHECK-NEXT: [5] - SiFiveP400IEXQ278# CHECK-NEXT: [6] - SiFiveP400Load79# CHECK-NEXT: [7] - SiFiveP400Store80# CHECK-NEXT: [8] - SiFiveP400VDiv81# CHECK-NEXT: [9] - SiFiveP400VEXQ082# CHECK-NEXT: [10] - SiFiveP400VFloatDiv83# CHECK-NEXT: [11] - SiFiveP400VLD84# CHECK-NEXT: [12] - SiFiveP400VST85 86# CHECK: Resource pressure per iteration:87# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]88# CHECK-NEXT: - - - - 4.00 - - - - 60.00 - - -89 90# CHECK: Resource pressure by instruction:91# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:92# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu93# CHECK-NEXT: - - - - - - - - - 1.00 - - - vclmul.vv v4, v8, v1294# CHECK-NEXT: - - - - - - - - - 1.00 - - - vclmul.vx v4, v8, a095# CHECK-NEXT: - - - - - - - - - 1.00 - - - vclmulh.vv v4, v8, v1296# CHECK-NEXT: - - - - - - - - - 1.00 - - - vclmulh.vx v4, v8, a097# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu98# CHECK-NEXT: - - - - - - - - - 2.00 - - - vclmul.vv v4, v8, v1299# CHECK-NEXT: - - - - - - - - - 2.00 - - - vclmul.vx v4, v8, a0100# CHECK-NEXT: - - - - - - - - - 2.00 - - - vclmulh.vv v4, v8, v12101# CHECK-NEXT: - - - - - - - - - 2.00 - - - vclmulh.vx v4, v8, a0102# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu103# CHECK-NEXT: - - - - - - - - - 4.00 - - - vclmul.vv v4, v8, v12104# CHECK-NEXT: - - - - - - - - - 4.00 - - - vclmul.vx v4, v8, a0105# CHECK-NEXT: - - - - - - - - - 4.00 - - - vclmulh.vv v4, v8, v12106# CHECK-NEXT: - - - - - - - - - 4.00 - - - vclmulh.vx v4, v8, a0107# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m8, tu, mu108# CHECK-NEXT: - - - - - - - - - 8.00 - - - vclmul.vv v8, v12, v24109# CHECK-NEXT: - - - - - - - - - 8.00 - - - vclmul.vx v8, v12, a0110# CHECK-NEXT: - - - - - - - - - 8.00 - - - vclmulh.vv v8, v12, v24111# CHECK-NEXT: - - - - - - - - - 8.00 - - - vclmulh.vx v8, v12, a0112 113