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1 2# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py3# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 < %s | FileCheck %s4 5vsetvli zero, zero, e8, mf8, tu, mu6vghsh.vv v4, v8, v127vgmul.vv v4, v88 9vsetvli zero, zero, e16, mf4, tu, mu10vghsh.vv v4, v8, v1211vgmul.vv v4, v812 13vsetvli zero, zero, e32, mf2, tu, mu14vghsh.vv v4, v8, v1215vgmul.vv v4, v816 17vsetvli zero, zero, e32, m1, tu, mu18vghsh.vv v4, v8, v1219vgmul.vv v4, v820 21vsetvli zero, zero, e32, m2, tu, mu22vghsh.vv v4, v8, v1223vgmul.vv v4, v824 25vsetvli zero, zero, e32, m4, tu, mu26vghsh.vv v4, v8, v1227vgmul.vv v4, v828 29vsetvli zero, zero, e32, m8, tu, mu30vghsh.vv v8, v16, v2431vgmul.vv v8, v1632 33# Show SEW does not matter34vsetvli zero, zero, e64, m4, tu, mu35vghsh.vv v4, v8, v1236vgmul.vv v4, v837 38# CHECK: Iterations: 139# CHECK-NEXT: Instructions: 2440# CHECK-NEXT: Total Cycles: 7641# CHECK-NEXT: Total uOps: 2442 43# CHECK: Dispatch Width: 344# CHECK-NEXT: uOps Per Cycle: 0.3245# CHECK-NEXT: IPC: 0.3246# CHECK-NEXT: Block RThroughput: 72.047 48# CHECK: Instruction Info:49# CHECK-NEXT: [1]: #uOps50# CHECK-NEXT: [2]: Latency51# CHECK-NEXT: [3]: RThroughput52# CHECK-NEXT: [4]: MayLoad53# CHECK-NEXT: [5]: MayStore54# CHECK-NEXT: [6]: HasSideEffects (U)55 56# CHECK: [1] [2] [3] [4] [5] [6] Instructions:57# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu58# CHECK-NEXT: 1 2 8.00 vghsh.vv v4, v8, v1259# CHECK-NEXT: 1 2 8.00 vgmul.vv v4, v860# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu61# CHECK-NEXT: 1 2 8.00 vghsh.vv v4, v8, v1262# CHECK-NEXT: 1 2 8.00 vgmul.vv v4, v863# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu64# CHECK-NEXT: 1 2 1.00 vghsh.vv v4, v8, v1265# CHECK-NEXT: 1 2 1.00 vgmul.vv v4, v866# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu67# CHECK-NEXT: 1 2 1.00 vghsh.vv v4, v8, v1268# CHECK-NEXT: 1 2 1.00 vgmul.vv v4, v869# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu70# CHECK-NEXT: 1 2 2.00 vghsh.vv v4, v8, v1271# CHECK-NEXT: 1 2 2.00 vgmul.vv v4, v872# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu73# CHECK-NEXT: 1 2 4.00 vghsh.vv v4, v8, v1274# CHECK-NEXT: 1 2 4.00 vgmul.vv v4, v875# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu76# CHECK-NEXT: 1 2 8.00 vghsh.vv v8, v16, v2477# CHECK-NEXT: 1 2 8.00 vgmul.vv v8, v1678# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu79# CHECK-NEXT: 1 2 4.00 vghsh.vv v4, v8, v1280# CHECK-NEXT: 1 2 4.00 vgmul.vv v4, v881 82# CHECK: Resources:83# CHECK-NEXT: [0] - SiFiveP400Div84# CHECK-NEXT: [1] - SiFiveP400FEXQ085# CHECK-NEXT: [2] - SiFiveP400FloatDiv86# CHECK-NEXT: [3] - SiFiveP400IEXQ087# CHECK-NEXT: [4] - SiFiveP400IEXQ188# CHECK-NEXT: [5] - SiFiveP400IEXQ289# CHECK-NEXT: [6] - SiFiveP400Load90# CHECK-NEXT: [7] - SiFiveP400Store91# CHECK-NEXT: [8] - SiFiveP400VDiv92# CHECK-NEXT: [9] - SiFiveP400VEXQ093# CHECK-NEXT: [10] - SiFiveP400VFloatDiv94# CHECK-NEXT: [11] - SiFiveP400VLD95# CHECK-NEXT: [12] - SiFiveP400VST96 97# CHECK: Resource pressure per iteration:98# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]99# CHECK-NEXT: - - - - 8.00 - - - - 72.00 - - -100 101# CHECK: Resource pressure by instruction:102# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:103# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu104# CHECK-NEXT: - - - - - - - - - 8.00 - - - vghsh.vv v4, v8, v12105# CHECK-NEXT: - - - - - - - - - 8.00 - - - vgmul.vv v4, v8106# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu107# CHECK-NEXT: - - - - - - - - - 8.00 - - - vghsh.vv v4, v8, v12108# CHECK-NEXT: - - - - - - - - - 8.00 - - - vgmul.vv v4, v8109# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu110# CHECK-NEXT: - - - - - - - - - 1.00 - - - vghsh.vv v4, v8, v12111# CHECK-NEXT: - - - - - - - - - 1.00 - - - vgmul.vv v4, v8112# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu113# CHECK-NEXT: - - - - - - - - - 1.00 - - - vghsh.vv v4, v8, v12114# CHECK-NEXT: - - - - - - - - - 1.00 - - - vgmul.vv v4, v8115# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu116# CHECK-NEXT: - - - - - - - - - 2.00 - - - vghsh.vv v4, v8, v12117# CHECK-NEXT: - - - - - - - - - 2.00 - - - vgmul.vv v4, v8118# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu119# CHECK-NEXT: - - - - - - - - - 4.00 - - - vghsh.vv v4, v8, v12120# CHECK-NEXT: - - - - - - - - - 4.00 - - - vgmul.vv v4, v8121# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu122# CHECK-NEXT: - - - - - - - - - 8.00 - - - vghsh.vv v8, v16, v24123# CHECK-NEXT: - - - - - - - - - 8.00 - - - vgmul.vv v8, v16124# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu125# CHECK-NEXT: - - - - - - - - - 4.00 - - - vghsh.vv v4, v8, v12126# CHECK-NEXT: - - - - - - - - - 4.00 - - - vgmul.vv v4, v8127 128