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1 2# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py3# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 < %s | FileCheck %s4 5# These instructions only support e326 7vsetvli zero, zero, e32, mf2, tu, mu8vsm3me.vv v4, v8, v129vsm3c.vi v4, v8, 810 11vsetvli zero, zero, e32, m1, tu, mu12vsm3me.vv v4, v8, v1213vsm3c.vi v4, v8, 814 15vsetvli zero, zero, e32, m2, tu, mu16vsm3me.vv v4, v8, v1217vsm3c.vi v4, v8, 818 19vsetvli zero, zero, e32, m4, tu, mu20vsm3me.vv v4, v8, v1221vsm3c.vi v4, v8, 822 23vsetvli zero, zero, e32, m8, tu, mu24vsm3me.vv v8, v16, v2425vsm3c.vi v8, v16, 826 27# CHECK: Iterations: 128# CHECK-NEXT: Instructions: 1529# CHECK-NEXT: Total Cycles: 2830# CHECK-NEXT: Total uOps: 1531 32# CHECK: Dispatch Width: 333# CHECK-NEXT: uOps Per Cycle: 0.5434# CHECK-NEXT: IPC: 0.5435# CHECK-NEXT: Block RThroughput: 25.036 37# CHECK: Instruction Info:38# CHECK-NEXT: [1]: #uOps39# CHECK-NEXT: [2]: Latency40# CHECK-NEXT: [3]: RThroughput41# CHECK-NEXT: [4]: MayLoad42# CHECK-NEXT: [5]: MayStore43# CHECK-NEXT: [6]: HasSideEffects (U)44 45# CHECK: [1] [2] [3] [4] [5] [6] Instructions:46# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu47# CHECK-NEXT: 1 6 1.00 vsm3me.vv v4, v8, v1248# CHECK-NEXT: 1 3 1.00 vsm3c.vi v4, v8, 849# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu50# CHECK-NEXT: 1 6 1.00 vsm3me.vv v4, v8, v1251# CHECK-NEXT: 1 3 1.00 vsm3c.vi v4, v8, 852# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu53# CHECK-NEXT: 1 6 2.00 vsm3me.vv v4, v8, v1254# CHECK-NEXT: 1 3 1.00 vsm3c.vi v4, v8, 855# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu56# CHECK-NEXT: 1 6 4.00 vsm3me.vv v4, v8, v1257# CHECK-NEXT: 1 3 2.00 vsm3c.vi v4, v8, 858# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu59# CHECK-NEXT: 1 6 8.00 vsm3me.vv v8, v16, v2460# CHECK-NEXT: 1 3 4.00 vsm3c.vi v8, v16, 861 62# CHECK: Resources:63# CHECK-NEXT: [0] - SiFiveP400Div64# CHECK-NEXT: [1] - SiFiveP400FEXQ065# CHECK-NEXT: [2] - SiFiveP400FloatDiv66# CHECK-NEXT: [3] - SiFiveP400IEXQ067# CHECK-NEXT: [4] - SiFiveP400IEXQ168# CHECK-NEXT: [5] - SiFiveP400IEXQ269# CHECK-NEXT: [6] - SiFiveP400Load70# CHECK-NEXT: [7] - SiFiveP400Store71# CHECK-NEXT: [8] - SiFiveP400VDiv72# CHECK-NEXT: [9] - SiFiveP400VEXQ073# CHECK-NEXT: [10] - SiFiveP400VFloatDiv74# CHECK-NEXT: [11] - SiFiveP400VLD75# CHECK-NEXT: [12] - SiFiveP400VST76 77# CHECK: Resource pressure per iteration:78# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]79# CHECK-NEXT: - - - - 5.00 - - - - 25.00 - - -80 81# CHECK: Resource pressure by instruction:82# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:83# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu84# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsm3me.vv v4, v8, v1285# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsm3c.vi v4, v8, 886# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu87# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsm3me.vv v4, v8, v1288# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsm3c.vi v4, v8, 889# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu90# CHECK-NEXT: - - - - - - - - - 2.00 - - - vsm3me.vv v4, v8, v1291# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsm3c.vi v4, v8, 892# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu93# CHECK-NEXT: - - - - - - - - - 4.00 - - - vsm3me.vv v4, v8, v1294# CHECK-NEXT: - - - - - - - - - 2.00 - - - vsm3c.vi v4, v8, 895# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu96# CHECK-NEXT: - - - - - - - - - 8.00 - - - vsm3me.vv v8, v16, v2497# CHECK-NEXT: - - - - - - - - - 4.00 - - - vsm3c.vi v8, v16, 898 99