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1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py2# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p550 -iterations=1 < %s | FileCheck %s3 4lw t0, 0(a0)5ld t0, 0(a0)6 7flw ft0, 0(a0)8fld ft0, 0(a0)9 10# CHECK: Iterations: 111# CHECK-NEXT: Instructions: 412# CHECK-NEXT: Total Cycles: 1113# CHECK-NEXT: Total uOps: 414 15# CHECK: Dispatch Width: 316# CHECK-NEXT: uOps Per Cycle: 0.3617# CHECK-NEXT: IPC: 0.3618# CHECK-NEXT: Block RThroughput: 4.019 20# CHECK: Instruction Info:21# CHECK-NEXT: [1]: #uOps22# CHECK-NEXT: [2]: Latency23# CHECK-NEXT: [3]: RThroughput24# CHECK-NEXT: [4]: MayLoad25# CHECK-NEXT: [5]: MayStore26# CHECK-NEXT: [6]: HasSideEffects (U)27 28# CHECK: [1] [2] [3] [4] [5] [6] Instructions:29# CHECK-NEXT: 1 4 1.00 * lw t0, 0(a0)30# CHECK-NEXT: 1 4 1.00 * ld t0, 0(a0)31# CHECK-NEXT: 1 5 1.00 * flw ft0, 0(a0)32# CHECK-NEXT: 1 5 1.00 * fld ft0, 0(a0)33 34# CHECK: Resources:35# CHECK-NEXT: [0] - SiFiveP500Div36# CHECK-NEXT: [1] - SiFiveP500FEXQ037# CHECK-NEXT: [2] - SiFiveP500FEXQ138# CHECK-NEXT: [3] - SiFiveP500FloatDiv39# CHECK-NEXT: [4] - SiFiveP500IEXQ040# CHECK-NEXT: [5] - SiFiveP500IEXQ141# CHECK-NEXT: [6] - SiFiveP500IEXQ242# CHECK-NEXT: [7] - SiFiveP500Load43# CHECK-NEXT: [8] - SiFiveP500Store44 45# CHECK: Resource pressure per iteration:46# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8]47# CHECK-NEXT: - - - - - - - 4.00 -48 49# CHECK: Resource pressure by instruction:50# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] Instructions:51# CHECK-NEXT: - - - - - - - 1.00 - lw t0, 0(a0)52# CHECK-NEXT: - - - - - - - 1.00 - ld t0, 0(a0)53# CHECK-NEXT: - - - - - - - 1.00 - flw ft0, 0(a0)54# CHECK-NEXT: - - - - - - - 1.00 - fld ft0, 0(a0)55