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1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py2# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 < %s | FileCheck %s3 4# These instructions only work with e645 6vsetvli zero, zero, e64, m1, tu, mu7vclmul.vv v4, v8, v128vclmul.vx v4, v8, a09vclmulh.vv v4, v8, v1210vclmulh.vx v4, v8, a011 12vsetvli zero, zero, e64, m2, tu, mu13vclmul.vv v4, v8, v1214vclmul.vx v4, v8, a015vclmulh.vv v4, v8, v1216vclmulh.vx v4, v8, a017 18vsetvli zero, zero, e64, m4, tu, mu19vclmul.vv v4, v8, v1220vclmul.vx v4, v8, a021vclmulh.vv v4, v8, v1222vclmulh.vx v4, v8, a023 24vsetvli zero, zero, e64, m8, tu, mu25vclmul.vv v8, v12, v2426vclmul.vx v8, v12, a027vclmulh.vv v8, v12, v2428vclmulh.vx v8, v12, a029 30# CHECK: Iterations: 131# CHECK-NEXT: Instructions: 2032# CHECK-NEXT: Total Cycles: 6433# CHECK-NEXT: Total uOps: 2034 35# CHECK: Dispatch Width: 436# CHECK-NEXT: uOps Per Cycle: 0.3137# CHECK-NEXT: IPC: 0.3138# CHECK-NEXT: Block RThroughput: 60.039 40# CHECK: Instruction Info:41# CHECK-NEXT: [1]: #uOps42# CHECK-NEXT: [2]: Latency43# CHECK-NEXT: [3]: RThroughput44# CHECK-NEXT: [4]: MayLoad45# CHECK-NEXT: [5]: MayStore46# CHECK-NEXT: [6]: HasSideEffects (U)47 48# CHECK: [1] [2] [3] [4] [5] [6] Instructions:49# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu50# CHECK-NEXT: 1 2 1.00 vclmul.vv v4, v8, v1251# CHECK-NEXT: 1 2 1.00 vclmul.vx v4, v8, a052# CHECK-NEXT: 1 2 1.00 vclmulh.vv v4, v8, v1253# CHECK-NEXT: 1 2 1.00 vclmulh.vx v4, v8, a054# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu55# CHECK-NEXT: 1 2 2.00 vclmul.vv v4, v8, v1256# CHECK-NEXT: 1 2 2.00 vclmul.vx v4, v8, a057# CHECK-NEXT: 1 2 2.00 vclmulh.vv v4, v8, v1258# CHECK-NEXT: 1 2 2.00 vclmulh.vx v4, v8, a059# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu60# CHECK-NEXT: 1 4 4.00 vclmul.vv v4, v8, v1261# CHECK-NEXT: 1 4 4.00 vclmul.vx v4, v8, a062# CHECK-NEXT: 1 4 4.00 vclmulh.vv v4, v8, v1263# CHECK-NEXT: 1 4 4.00 vclmulh.vx v4, v8, a064# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu65# CHECK-NEXT: 1 8 8.00 vclmul.vv v8, v12, v2466# CHECK-NEXT: 1 8 8.00 vclmul.vx v8, v12, a067# CHECK-NEXT: 1 8 8.00 vclmulh.vv v8, v12, v2468# CHECK-NEXT: 1 8 8.00 vclmulh.vx v8, v12, a069 70# CHECK: Resources:71# CHECK-NEXT: [0] - SiFiveP600Div72# CHECK-NEXT: [1] - SiFiveP600FEXQ073# CHECK-NEXT: [2] - SiFiveP600FEXQ174# CHECK-NEXT: [3] - SiFiveP600FloatDiv75# CHECK-NEXT: [4] - SiFiveP600IEXQ076# CHECK-NEXT: [5] - SiFiveP600IEXQ177# CHECK-NEXT: [6] - SiFiveP600IEXQ278# CHECK-NEXT: [7] - SiFiveP600IEXQ379# CHECK-NEXT: [8.0] - SiFiveP600LDST80# CHECK-NEXT: [8.1] - SiFiveP600LDST81# CHECK-NEXT: [9] - SiFiveP600VDiv82# CHECK-NEXT: [10] - SiFiveP600VEXQ083# CHECK-NEXT: [11] - SiFiveP600VEXQ184# CHECK-NEXT: [12] - SiFiveP600VFloatDiv85# CHECK-NEXT: [13] - SiFiveP600VLD86# CHECK-NEXT: [14] - SiFiveP600VST87 88# CHECK: Resource pressure per iteration:89# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]90# CHECK-NEXT: - - - - 4.00 - - - - - - 60.00 - - - -91 92# CHECK: Resource pressure by instruction:93# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions:94# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu95# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vclmul.vv v4, v8, v1296# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vclmul.vx v4, v8, a097# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vclmulh.vv v4, v8, v1298# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vclmulh.vx v4, v8, a099# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu100# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vclmul.vv v4, v8, v12101# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vclmul.vx v4, v8, a0102# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vclmulh.vv v4, v8, v12103# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vclmulh.vx v4, v8, a0104# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu105# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vclmul.vv v4, v8, v12106# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vclmul.vx v4, v8, a0107# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vclmulh.vv v4, v8, v12108# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vclmulh.vx v4, v8, a0109# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m8, tu, mu110# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vclmul.vv v8, v12, v24111# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vclmul.vx v8, v12, a0112# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vclmulh.vv v8, v12, v24113# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vclmulh.vx v8, v12, a0114