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1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py2# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 < %s | FileCheck %s3 4vsetvli zero, zero, e8, mf8, tu, mu5vghsh.vv v4, v8, v126vgmul.vv v4, v87 8vsetvli zero, zero, e16, mf4, tu, mu9vghsh.vv v4, v8, v1210vgmul.vv v4, v811 12vsetvli zero, zero, e32, mf2, tu, mu13vghsh.vv v4, v8, v1214vgmul.vv v4, v815 16vsetvli zero, zero, e32, m1, tu, mu17vghsh.vv v4, v8, v1218vgmul.vv v4, v819 20vsetvli zero, zero, e32, m2, tu, mu21vghsh.vv v4, v8, v1222vgmul.vv v4, v823 24vsetvli zero, zero, e32, m4, tu, mu25vghsh.vv v4, v8, v1226vgmul.vv v4, v827 28vsetvli zero, zero, e32, m8, tu, mu29vghsh.vv v8, v16, v2430vgmul.vv v8, v1631 32# Show SEW does not matter33vsetvli zero, zero, e64, m4, tu, mu34vghsh.vv v4, v8, v1235vgmul.vv v4, v836 37# CHECK: Iterations: 138# CHECK-NEXT: Instructions: 2439# CHECK-NEXT: Total Cycles: 7840# CHECK-NEXT: Total uOps: 2441 42# CHECK: Dispatch Width: 443# CHECK-NEXT: uOps Per Cycle: 0.3144# CHECK-NEXT: IPC: 0.3145# CHECK-NEXT: Block RThroughput: 72.046 47# CHECK: Instruction Info:48# CHECK-NEXT: [1]: #uOps49# CHECK-NEXT: [2]: Latency50# CHECK-NEXT: [3]: RThroughput51# CHECK-NEXT: [4]: MayLoad52# CHECK-NEXT: [5]: MayStore53# CHECK-NEXT: [6]: HasSideEffects (U)54 55# CHECK: [1] [2] [3] [4] [5] [6] Instructions:56# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu57# CHECK-NEXT: 1 8 8.00 vghsh.vv v4, v8, v1258# CHECK-NEXT: 1 8 8.00 vgmul.vv v4, v859# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu60# CHECK-NEXT: 1 8 8.00 vghsh.vv v4, v8, v1261# CHECK-NEXT: 1 8 8.00 vgmul.vv v4, v862# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu63# CHECK-NEXT: 1 2 1.00 vghsh.vv v4, v8, v1264# CHECK-NEXT: 1 2 1.00 vgmul.vv v4, v865# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu66# CHECK-NEXT: 1 2 1.00 vghsh.vv v4, v8, v1267# CHECK-NEXT: 1 2 1.00 vgmul.vv v4, v868# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu69# CHECK-NEXT: 1 2 2.00 vghsh.vv v4, v8, v1270# CHECK-NEXT: 1 2 2.00 vgmul.vv v4, v871# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu72# CHECK-NEXT: 1 4 4.00 vghsh.vv v4, v8, v1273# CHECK-NEXT: 1 4 4.00 vgmul.vv v4, v874# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu75# CHECK-NEXT: 1 8 8.00 vghsh.vv v8, v16, v2476# CHECK-NEXT: 1 8 8.00 vgmul.vv v8, v1677# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu78# CHECK-NEXT: 1 4 4.00 vghsh.vv v4, v8, v1279# CHECK-NEXT: 1 4 4.00 vgmul.vv v4, v880 81# CHECK: Resources:82# CHECK-NEXT: [0] - SiFiveP600Div83# CHECK-NEXT: [1] - SiFiveP600FEXQ084# CHECK-NEXT: [2] - SiFiveP600FEXQ185# CHECK-NEXT: [3] - SiFiveP600FloatDiv86# CHECK-NEXT: [4] - SiFiveP600IEXQ087# CHECK-NEXT: [5] - SiFiveP600IEXQ188# CHECK-NEXT: [6] - SiFiveP600IEXQ289# CHECK-NEXT: [7] - SiFiveP600IEXQ390# CHECK-NEXT: [8.0] - SiFiveP600LDST91# CHECK-NEXT: [8.1] - SiFiveP600LDST92# CHECK-NEXT: [9] - SiFiveP600VDiv93# CHECK-NEXT: [10] - SiFiveP600VEXQ094# CHECK-NEXT: [11] - SiFiveP600VEXQ195# CHECK-NEXT: [12] - SiFiveP600VFloatDiv96# CHECK-NEXT: [13] - SiFiveP600VLD97# CHECK-NEXT: [14] - SiFiveP600VST98 99# CHECK: Resource pressure per iteration:100# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]101# CHECK-NEXT: - - - - 8.00 - - - - - - 72.00 - - - -102 103# CHECK: Resource pressure by instruction:104# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions:105# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu106# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vghsh.vv v4, v8, v12107# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vgmul.vv v4, v8108# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu109# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vghsh.vv v4, v8, v12110# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vgmul.vv v4, v8111# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu112# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vghsh.vv v4, v8, v12113# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vgmul.vv v4, v8114# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu115# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vghsh.vv v4, v8, v12116# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vgmul.vv v4, v8117# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu118# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vghsh.vv v4, v8, v12119# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vgmul.vv v4, v8120# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu121# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vghsh.vv v4, v8, v12122# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vgmul.vv v4, v8123# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu124# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vghsh.vv v8, v16, v24125# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vgmul.vv v8, v16126# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu127# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vghsh.vv v4, v8, v12128# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vgmul.vv v4, v8129