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1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py2# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 < %s | FileCheck %s3 4# These instructions only support e325 6vsetvli zero, zero, e32, mf2, tu, mu7vsm3me.vv v4, v8, v128vsm3c.vi v4, v8, 89 10vsetvli zero, zero, e32, m1, tu, mu11vsm3me.vv v4, v8, v1212vsm3c.vi v4, v8, 813 14vsetvli zero, zero, e32, m2, tu, mu15vsm3me.vv v4, v8, v1216vsm3c.vi v4, v8, 817 18vsetvli zero, zero, e32, m4, tu, mu19vsm3me.vv v4, v8, v1220vsm3c.vi v4, v8, 821 22vsetvli zero, zero, e32, m8, tu, mu23vsm3me.vv v8, v16, v2424vsm3c.vi v8, v16, 825 26# CHECK: Iterations: 127# CHECK-NEXT: Instructions: 1528# CHECK-NEXT: Total Cycles: 2829# CHECK-NEXT: Total uOps: 1530 31# CHECK: Dispatch Width: 432# CHECK-NEXT: uOps Per Cycle: 0.5433# CHECK-NEXT: IPC: 0.5434# CHECK-NEXT: Block RThroughput: 25.035 36# CHECK: Instruction Info:37# CHECK-NEXT: [1]: #uOps38# CHECK-NEXT: [2]: Latency39# CHECK-NEXT: [3]: RThroughput40# CHECK-NEXT: [4]: MayLoad41# CHECK-NEXT: [5]: MayStore42# CHECK-NEXT: [6]: HasSideEffects (U)43 44# CHECK: [1] [2] [3] [4] [5] [6] Instructions:45# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu46# CHECK-NEXT: 1 6 1.00 vsm3me.vv v4, v8, v1247# CHECK-NEXT: 1 3 1.00 vsm3c.vi v4, v8, 848# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu49# CHECK-NEXT: 1 6 1.00 vsm3me.vv v4, v8, v1250# CHECK-NEXT: 1 3 1.00 vsm3c.vi v4, v8, 851# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu52# CHECK-NEXT: 1 6 2.00 vsm3me.vv v4, v8, v1253# CHECK-NEXT: 1 3 1.00 vsm3c.vi v4, v8, 854# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu55# CHECK-NEXT: 1 6 4.00 vsm3me.vv v4, v8, v1256# CHECK-NEXT: 1 3 2.00 vsm3c.vi v4, v8, 857# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu58# CHECK-NEXT: 1 6 8.00 vsm3me.vv v8, v16, v2459# CHECK-NEXT: 1 3 4.00 vsm3c.vi v8, v16, 860 61# CHECK: Resources:62# CHECK-NEXT: [0] - SiFiveP600Div63# CHECK-NEXT: [1] - SiFiveP600FEXQ064# CHECK-NEXT: [2] - SiFiveP600FEXQ165# CHECK-NEXT: [3] - SiFiveP600FloatDiv66# CHECK-NEXT: [4] - SiFiveP600IEXQ067# CHECK-NEXT: [5] - SiFiveP600IEXQ168# CHECK-NEXT: [6] - SiFiveP600IEXQ269# CHECK-NEXT: [7] - SiFiveP600IEXQ370# CHECK-NEXT: [8.0] - SiFiveP600LDST71# CHECK-NEXT: [8.1] - SiFiveP600LDST72# CHECK-NEXT: [9] - SiFiveP600VDiv73# CHECK-NEXT: [10] - SiFiveP600VEXQ074# CHECK-NEXT: [11] - SiFiveP600VEXQ175# CHECK-NEXT: [12] - SiFiveP600VFloatDiv76# CHECK-NEXT: [13] - SiFiveP600VLD77# CHECK-NEXT: [14] - SiFiveP600VST78 79# CHECK: Resource pressure per iteration:80# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]81# CHECK-NEXT: - - - - 5.00 - - - - - - 25.00 - - - -82 83# CHECK: Resource pressure by instruction:84# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions:85# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu86# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vsm3me.vv v4, v8, v1287# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vsm3c.vi v4, v8, 888# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu89# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vsm3me.vv v4, v8, v1290# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vsm3c.vi v4, v8, 891# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu92# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vsm3me.vv v4, v8, v1293# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vsm3c.vi v4, v8, 894# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu95# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vsm3me.vv v4, v8, v1296# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vsm3c.vi v4, v8, 897# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu98# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vsm3me.vv v8, v16, v2499# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vsm3c.vi v8, v16, 8100