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1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py2# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870 -iterations=1 -instruction-tables=full < %s | FileCheck %s3# COM: Check if we're only bypassing on rs3 of FMADD (i.e. addend) or not.4# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870 -iterations=1 -timeline < %s | FileCheck %s --check-prefix=TIMELINE5 6fmadd.s fa0, fa0, fa1, fa27fmadd.s fa2, fa2, fa1, fa08fmadd.s ft1, ft1, fa2, ft09 10fmadd.d fa0, fa0, fa1, fa211fmadd.d fa2, fa2, fa1, fa012fmadd.d ft1, ft1, fa2, ft013 14fmadd.h fa0, fa0, fa1, fa215fmadd.h fa2, fa2, fa1, fa016fmadd.h ft1, ft1, fa2, ft017 18# TIMELINE: Iterations: 119# TIMELINE-NEXT: Instructions: 920# TIMELINE-NEXT: Total Cycles: 2521# TIMELINE-NEXT: Total uOps: 922 23# CHECK: Resources:24# CHECK-NEXT: [0] - SiFiveP800Branch:2 SiFiveP800IEXQ4, SiFiveP800IEXQ525# CHECK-NEXT: [1] - SiFiveP800Div:126# CHECK-NEXT: [2] - SiFiveP800FEXQ0:127# CHECK-NEXT: [3] - SiFiveP800FEXQ1:128# CHECK-NEXT: [4] - SiFiveP800FloatArith:2 SiFiveP800FEXQ0, SiFiveP800FEXQ129# CHECK-NEXT: [5] - SiFiveP800FloatDiv:130# CHECK-NEXT: [6] - SiFiveP800IEXQ0:131# CHECK-NEXT: [7] - SiFiveP800IEXQ1:132# CHECK-NEXT: [8] - SiFiveP800IEXQ2:133# CHECK-NEXT: [9] - SiFiveP800IEXQ3:134# CHECK-NEXT: [10] - SiFiveP800IEXQ4:135# CHECK-NEXT: [11] - SiFiveP800IEXQ5:136# CHECK-NEXT: [12] - SiFiveP800IntArith:4 SiFiveP800IEXQ0, SiFiveP800IEXQ1, SiFiveP800IEXQ2, SiFiveP800IEXQ337# CHECK-NEXT: [13] - SiFiveP800LD:138# CHECK-NEXT: [14] - SiFiveP800LDST:239# CHECK-NEXT: [15] - SiFiveP800Load:3 SiFiveP800LDST, SiFiveP800LDST, SiFiveP800LD40# CHECK-NEXT: [16] - SiFiveP800Mul:2 SiFiveP800IEXQ1, SiFiveP800IEXQ341# CHECK-NEXT: [17] - SiFiveP800VDiv:142# CHECK-NEXT: [18] - SiFiveP800VEXQ0:143# CHECK-NEXT: [19] - SiFiveP800VEXQ1:144# CHECK-NEXT: [20] - SiFiveP800VFloatDiv:145# CHECK-NEXT: [21] - SiFiveP800VLD:146# CHECK-NEXT: [22] - SiFiveP800VST:147# CHECK-NEXT: [23] - SiFiveP800VectorArith:2 SiFiveP800VEXQ0, SiFiveP800VEXQ148 49# TIMELINE: Dispatch Width: 650# TIMELINE-NEXT: uOps Per Cycle: 0.3651# TIMELINE-NEXT: IPC: 0.3652# TIMELINE-NEXT: Block RThroughput: 4.553 54# CHECK: Instruction Info:55# CHECK-NEXT: [1]: #uOps56# CHECK-NEXT: [2]: Latency57# CHECK-NEXT: [3]: RThroughput58# CHECK-NEXT: [4]: MayLoad59# CHECK-NEXT: [5]: MayStore60# CHECK-NEXT: [6]: HasSideEffects (U)61# CHECK-NEXT: [7]: Bypass Latency62# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])63# CHECK-NEXT: [9]: LLVM Opcode Name64 65# TIMELINE: Instruction Info:66# TIMELINE-NEXT: [1]: #uOps67# TIMELINE-NEXT: [2]: Latency68# TIMELINE-NEXT: [3]: RThroughput69# TIMELINE-NEXT: [4]: MayLoad70# TIMELINE-NEXT: [5]: MayStore71# TIMELINE-NEXT: [6]: HasSideEffects (U)72 73# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:74# CHECK-NEXT: 1 4 0.50 2 SiFiveP800FloatArith FMADD_S fmadd.s fa0, fa0, fa1, fa275# CHECK-NEXT: 1 4 0.50 2 SiFiveP800FloatArith FMADD_S fmadd.s fa2, fa2, fa1, fa076# CHECK-NEXT: 1 4 0.50 2 SiFiveP800FloatArith FMADD_S fmadd.s ft1, ft1, fa2, ft077# CHECK-NEXT: 1 4 0.50 2 SiFiveP800FloatArith FMADD_D fmadd.d fa0, fa0, fa1, fa278# CHECK-NEXT: 1 4 0.50 2 SiFiveP800FloatArith FMADD_D fmadd.d fa2, fa2, fa1, fa079# CHECK-NEXT: 1 4 0.50 2 SiFiveP800FloatArith FMADD_D fmadd.d ft1, ft1, fa2, ft080# CHECK-NEXT: 1 4 0.50 2 SiFiveP800FloatArith FMADD_H fmadd.h fa0, fa0, fa1, fa281# CHECK-NEXT: 1 4 0.50 2 SiFiveP800FloatArith FMADD_H fmadd.h fa2, fa2, fa1, fa082# CHECK-NEXT: 1 4 0.50 2 SiFiveP800FloatArith FMADD_H fmadd.h ft1, ft1, fa2, ft083 84# TIMELINE: [1] [2] [3] [4] [5] [6] Instructions:85# TIMELINE-NEXT: 1 4 0.50 fmadd.s fa0, fa0, fa1, fa286# TIMELINE-NEXT: 1 4 0.50 fmadd.s fa2, fa2, fa1, fa087# TIMELINE-NEXT: 1 4 0.50 fmadd.s ft1, ft1, fa2, ft088# TIMELINE-NEXT: 1 4 0.50 fmadd.d fa0, fa0, fa1, fa289# TIMELINE-NEXT: 1 4 0.50 fmadd.d fa2, fa2, fa1, fa090# TIMELINE-NEXT: 1 4 0.50 fmadd.d ft1, ft1, fa2, ft091# TIMELINE-NEXT: 1 4 0.50 fmadd.h fa0, fa0, fa1, fa292# TIMELINE-NEXT: 1 4 0.50 fmadd.h fa2, fa2, fa1, fa093# TIMELINE-NEXT: 1 4 0.50 fmadd.h ft1, ft1, fa2, ft094 95# CHECK: Resources:96# CHECK-NEXT: [0] - SiFiveP800Div97# CHECK-NEXT: [1] - SiFiveP800FEXQ098# CHECK-NEXT: [2] - SiFiveP800FEXQ199# CHECK-NEXT: [3] - SiFiveP800FloatDiv100# CHECK-NEXT: [4] - SiFiveP800IEXQ0101# CHECK-NEXT: [5] - SiFiveP800IEXQ1102# CHECK-NEXT: [6] - SiFiveP800IEXQ2103# CHECK-NEXT: [7] - SiFiveP800IEXQ3104# CHECK-NEXT: [8] - SiFiveP800IEXQ4105# CHECK-NEXT: [9] - SiFiveP800IEXQ5106# CHECK-NEXT: [10] - SiFiveP800LD107# CHECK-NEXT: [11.0] - SiFiveP800LDST108# CHECK-NEXT: [11.1] - SiFiveP800LDST109# CHECK-NEXT: [12] - SiFiveP800VDiv110# CHECK-NEXT: [13] - SiFiveP800VEXQ0111# CHECK-NEXT: [14] - SiFiveP800VEXQ1112# CHECK-NEXT: [15] - SiFiveP800VFloatDiv113# CHECK-NEXT: [16] - SiFiveP800VLD114# CHECK-NEXT: [17] - SiFiveP800VST115 116# TIMELINE: Resources:117# TIMELINE-NEXT: [0] - SiFiveP800Div118# TIMELINE-NEXT: [1] - SiFiveP800FEXQ0119# TIMELINE-NEXT: [2] - SiFiveP800FEXQ1120# TIMELINE-NEXT: [3] - SiFiveP800FloatDiv121# TIMELINE-NEXT: [4] - SiFiveP800IEXQ0122# TIMELINE-NEXT: [5] - SiFiveP800IEXQ1123# TIMELINE-NEXT: [6] - SiFiveP800IEXQ2124# TIMELINE-NEXT: [7] - SiFiveP800IEXQ3125# TIMELINE-NEXT: [8] - SiFiveP800IEXQ4126# TIMELINE-NEXT: [9] - SiFiveP800IEXQ5127# TIMELINE-NEXT: [10] - SiFiveP800LD128# TIMELINE-NEXT: [11.0] - SiFiveP800LDST129# TIMELINE-NEXT: [11.1] - SiFiveP800LDST130# TIMELINE-NEXT: [12] - SiFiveP800VDiv131# TIMELINE-NEXT: [13] - SiFiveP800VEXQ0132# TIMELINE-NEXT: [14] - SiFiveP800VEXQ1133# TIMELINE-NEXT: [15] - SiFiveP800VFloatDiv134# TIMELINE-NEXT: [16] - SiFiveP800VLD135# TIMELINE-NEXT: [17] - SiFiveP800VST136 137# CHECK: Resource pressure per iteration:138# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [12] [13] [14] [15] [16] [17]139# CHECK-NEXT: - 4.50 4.50 - - - - - - - - - - - - - - - -140 141# TIMELINE: Resource pressure per iteration:142# TIMELINE-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [12] [13] [14] [15] [16] [17]143# TIMELINE-NEXT: - 4.00 5.00 - - - - - - - - - - - - - - - -144 145# CHECK: Resource pressure by instruction:146# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [12] [13] [14] [15] [16] [17] Instructions:147# CHECK-NEXT: - 0.50 0.50 - - - - - - - - - - - - - - - - fmadd.s fa0, fa0, fa1, fa2148# CHECK-NEXT: - 0.50 0.50 - - - - - - - - - - - - - - - - fmadd.s fa2, fa2, fa1, fa0149# CHECK-NEXT: - 0.50 0.50 - - - - - - - - - - - - - - - - fmadd.s ft1, ft1, fa2, ft0150# CHECK-NEXT: - 0.50 0.50 - - - - - - - - - - - - - - - - fmadd.d fa0, fa0, fa1, fa2151# CHECK-NEXT: - 0.50 0.50 - - - - - - - - - - - - - - - - fmadd.d fa2, fa2, fa1, fa0152# CHECK-NEXT: - 0.50 0.50 - - - - - - - - - - - - - - - - fmadd.d ft1, ft1, fa2, ft0153# CHECK-NEXT: - 0.50 0.50 - - - - - - - - - - - - - - - - fmadd.h fa0, fa0, fa1, fa2154# CHECK-NEXT: - 0.50 0.50 - - - - - - - - - - - - - - - - fmadd.h fa2, fa2, fa1, fa0155# CHECK-NEXT: - 0.50 0.50 - - - - - - - - - - - - - - - - fmadd.h ft1, ft1, fa2, ft0156 157# TIMELINE: Resource pressure by instruction:158# TIMELINE-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [12] [13] [14] [15] [16] [17] Instructions:159# TIMELINE-NEXT: - - 1.00 - - - - - - - - - - - - - - - - fmadd.s fa0, fa0, fa1, fa2160# TIMELINE-NEXT: - 1.00 - - - - - - - - - - - - - - - - - fmadd.s fa2, fa2, fa1, fa0161# TIMELINE-NEXT: - - 1.00 - - - - - - - - - - - - - - - - fmadd.s ft1, ft1, fa2, ft0162# TIMELINE-NEXT: - 1.00 - - - - - - - - - - - - - - - - - fmadd.d fa0, fa0, fa1, fa2163# TIMELINE-NEXT: - - 1.00 - - - - - - - - - - - - - - - - fmadd.d fa2, fa2, fa1, fa0164# TIMELINE-NEXT: - 1.00 - - - - - - - - - - - - - - - - - fmadd.d ft1, ft1, fa2, ft0165# TIMELINE-NEXT: - - 1.00 - - - - - - - - - - - - - - - - fmadd.h fa0, fa0, fa1, fa2166# TIMELINE-NEXT: - 1.00 - - - - - - - - - - - - - - - - - fmadd.h fa2, fa2, fa1, fa0167# TIMELINE-NEXT: - - 1.00 - - - - - - - - - - - - - - - - fmadd.h ft1, ft1, fa2, ft0168 169# TIMELINE: Timeline view:170# TIMELINE-NEXT: 0123456789171# TIMELINE-NEXT: Index 0123456789 01234172 173# TIMELINE: [0,0] DeeeeER . . . . fmadd.s fa0, fa0, fa1, fa2174# TIMELINE-NEXT: [0,1] D==eeeeER . . . . fmadd.s fa2, fa2, fa1, fa0175# TIMELINE-NEXT: [0,2] D======eeeeER . . . fmadd.s ft1, ft1, fa2, ft0176# TIMELINE-NEXT: [0,3] D======eeeeER . . . fmadd.d fa0, fa0, fa1, fa2177# TIMELINE-NEXT: [0,4] D========eeeeER. . . fmadd.d fa2, fa2, fa1, fa0178# TIMELINE-NEXT: [0,5] D============eeeeER . . fmadd.d ft1, ft1, fa2, ft0179# TIMELINE-NEXT: [0,6] .D===========eeeeER . . fmadd.h fa0, fa0, fa1, fa2180# TIMELINE-NEXT: [0,7] .D=============eeeeER . fmadd.h fa2, fa2, fa1, fa0181# TIMELINE-NEXT: [0,8] .D=================eeeeER fmadd.h ft1, ft1, fa2, ft0182 183# TIMELINE: Average Wait times (based on the timeline view):184# TIMELINE-NEXT: [0]: Executions185# TIMELINE-NEXT: [1]: Average time spent waiting in a scheduler's queue186# TIMELINE-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready187# TIMELINE-NEXT: [3]: Average time elapsed from WB until retire stage188 189# TIMELINE: [0] [1] [2] [3]190# TIMELINE-NEXT: 0. 1 1.0 1.0 0.0 fmadd.s fa0, fa0, fa1, fa2191# TIMELINE-NEXT: 1. 1 3.0 0.0 0.0 fmadd.s fa2, fa2, fa1, fa0192# TIMELINE-NEXT: 2. 1 7.0 0.0 0.0 fmadd.s ft1, ft1, fa2, ft0193# TIMELINE-NEXT: 3. 1 7.0 0.0 0.0 fmadd.d fa0, fa0, fa1, fa2194# TIMELINE-NEXT: 4. 1 9.0 0.0 0.0 fmadd.d fa2, fa2, fa1, fa0195# TIMELINE-NEXT: 5. 1 13.0 0.0 0.0 fmadd.d ft1, ft1, fa2, ft0196# TIMELINE-NEXT: 6. 1 12.0 0.0 0.0 fmadd.h fa0, fa0, fa1, fa2197# TIMELINE-NEXT: 7. 1 14.0 0.0 0.0 fmadd.h fa2, fa2, fa1, fa0198# TIMELINE-NEXT: 8. 1 18.0 0.0 0.0 fmadd.h ft1, ft1, fa2, ft0199# TIMELINE-NEXT: 1 9.3 0.1 0.0 <total>200