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1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py2# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870 -iterations=1 -instruction-tables=full < %s | FileCheck %s3 4lw t0, 0(a0)5ld t0, 0(a0)6 7flh ft0, 0(a0)8flw ft0, 0(a0)9fld ft0, 0(a0)10 11# CHECK: Resources:12# CHECK-NEXT: [0] - SiFiveP800Branch:2 SiFiveP800IEXQ4, SiFiveP800IEXQ513# CHECK-NEXT: [1] - SiFiveP800Div:114# CHECK-NEXT: [2] - SiFiveP800FEXQ0:115# CHECK-NEXT: [3] - SiFiveP800FEXQ1:116# CHECK-NEXT: [4] - SiFiveP800FloatArith:2 SiFiveP800FEXQ0, SiFiveP800FEXQ117# CHECK-NEXT: [5] - SiFiveP800FloatDiv:118# CHECK-NEXT: [6] - SiFiveP800IEXQ0:119# CHECK-NEXT: [7] - SiFiveP800IEXQ1:120# CHECK-NEXT: [8] - SiFiveP800IEXQ2:121# CHECK-NEXT: [9] - SiFiveP800IEXQ3:122# CHECK-NEXT: [10] - SiFiveP800IEXQ4:123# CHECK-NEXT: [11] - SiFiveP800IEXQ5:124# CHECK-NEXT: [12] - SiFiveP800IntArith:4 SiFiveP800IEXQ0, SiFiveP800IEXQ1, SiFiveP800IEXQ2, SiFiveP800IEXQ325# CHECK-NEXT: [13] - SiFiveP800LD:126# CHECK-NEXT: [14] - SiFiveP800LDST:227# CHECK-NEXT: [15] - SiFiveP800Load:3 SiFiveP800LDST, SiFiveP800LDST, SiFiveP800LD28# CHECK-NEXT: [16] - SiFiveP800Mul:2 SiFiveP800IEXQ1, SiFiveP800IEXQ329# CHECK-NEXT: [17] - SiFiveP800VDiv:130# CHECK-NEXT: [18] - SiFiveP800VEXQ0:131# CHECK-NEXT: [19] - SiFiveP800VEXQ1:132# CHECK-NEXT: [20] - SiFiveP800VFloatDiv:133# CHECK-NEXT: [21] - SiFiveP800VLD:134# CHECK-NEXT: [22] - SiFiveP800VST:135# CHECK-NEXT: [23] - SiFiveP800VectorArith:2 SiFiveP800VEXQ0, SiFiveP800VEXQ136 37# CHECK: Instruction Info:38# CHECK-NEXT: [1]: #uOps39# CHECK-NEXT: [2]: Latency40# CHECK-NEXT: [3]: RThroughput41# CHECK-NEXT: [4]: MayLoad42# CHECK-NEXT: [5]: MayStore43# CHECK-NEXT: [6]: HasSideEffects (U)44# CHECK-NEXT: [7]: Bypass Latency45# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])46# CHECK-NEXT: [9]: LLVM Opcode Name47 48# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:49# CHECK-NEXT: 1 4 0.33 * 4 SiFiveP800Load LW lw t0, 0(a0)50# CHECK-NEXT: 1 4 0.33 * 4 SiFiveP800Load LD ld t0, 0(a0)51# CHECK-NEXT: 1 5 0.33 * 5 SiFiveP800Load FLH flh ft0, 0(a0)52# CHECK-NEXT: 1 5 0.33 * 5 SiFiveP800Load FLW flw ft0, 0(a0)53# CHECK-NEXT: 1 5 0.33 * 5 SiFiveP800Load FLD fld ft0, 0(a0)54 55# CHECK: Resources:56# CHECK-NEXT: [0] - SiFiveP800Div57# CHECK-NEXT: [1] - SiFiveP800FEXQ058# CHECK-NEXT: [2] - SiFiveP800FEXQ159# CHECK-NEXT: [3] - SiFiveP800FloatDiv60# CHECK-NEXT: [4] - SiFiveP800IEXQ061# CHECK-NEXT: [5] - SiFiveP800IEXQ162# CHECK-NEXT: [6] - SiFiveP800IEXQ263# CHECK-NEXT: [7] - SiFiveP800IEXQ364# CHECK-NEXT: [8] - SiFiveP800IEXQ465# CHECK-NEXT: [9] - SiFiveP800IEXQ566# CHECK-NEXT: [10] - SiFiveP800LD67# CHECK-NEXT: [11.0] - SiFiveP800LDST68# CHECK-NEXT: [11.1] - SiFiveP800LDST69# CHECK-NEXT: [12] - SiFiveP800VDiv70# CHECK-NEXT: [13] - SiFiveP800VEXQ071# CHECK-NEXT: [14] - SiFiveP800VEXQ172# CHECK-NEXT: [15] - SiFiveP800VFloatDiv73# CHECK-NEXT: [16] - SiFiveP800VLD74# CHECK-NEXT: [17] - SiFiveP800VST75 76# CHECK: Resource pressure per iteration:77# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [12] [13] [14] [15] [16] [17]78# CHECK-NEXT: - - - - - - - - - - 1.67 1.67 1.67 - - - - - -79 80# CHECK: Resource pressure by instruction:81# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [12] [13] [14] [15] [16] [17] Instructions:82# CHECK-NEXT: - - - - - - - - - - 0.33 0.33 0.33 - - - - - - lw t0, 0(a0)83# CHECK-NEXT: - - - - - - - - - - 0.33 0.33 0.33 - - - - - - ld t0, 0(a0)84# CHECK-NEXT: - - - - - - - - - - 0.33 0.33 0.33 - - - - - - flh ft0, 0(a0)85# CHECK-NEXT: - - - - - - - - - - 0.33 0.33 0.33 - - - - - - flw ft0, 0(a0)86# CHECK-NEXT: - - - - - - - - - - 0.33 0.33 0.33 - - - - - - fld ft0, 0(a0)87