152 lines · plain
1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py2# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870 -iterations=1 -instruction-tables=full < %s | FileCheck %s3 4vsetvli zero, zero, e32, m1, ta, ma5 6vmslt.vv v0, v4, v207vmsle.vv v8, v4, v208vmsgt.vv v8, v20, v49vmsge.vv v8, v20, v410vmseq.vv v8, v4, v2011vmsne.vv v8, v4, v2012vmsltu.vv v8, v4, v2013vmsleu.vv v8, v4, v2014vmsgtu.vv v8, v20, v415vmsgeu.vv v8, v20, v416 17vmflt.vv v0, v4, v2018vmfle.vv v8, v4, v2019vmfgt.vv v8, v20, v420vmfge.vv v8, v20, v421vmfeq.vv v8, v4, v2022vmfne.vv v8, v4, v2023 24vmadc.vv v8, v4, v2025vmsbc.vv v8, v4, v2026 27vfirst.m a2, v428vpopc.m a2, v429 30viota.m v8, v431 32vmsbf.m v8, v433vmsif.m v8, v434vmsof.m v8, v435 36# CHECK: Resources:37# CHECK-NEXT: [0] - SiFiveP800Branch:2 SiFiveP800IEXQ4, SiFiveP800IEXQ538# CHECK-NEXT: [1] - SiFiveP800Div:139# CHECK-NEXT: [2] - SiFiveP800FEXQ0:140# CHECK-NEXT: [3] - SiFiveP800FEXQ1:141# CHECK-NEXT: [4] - SiFiveP800FloatArith:2 SiFiveP800FEXQ0, SiFiveP800FEXQ142# CHECK-NEXT: [5] - SiFiveP800FloatDiv:143# CHECK-NEXT: [6] - SiFiveP800IEXQ0:144# CHECK-NEXT: [7] - SiFiveP800IEXQ1:145# CHECK-NEXT: [8] - SiFiveP800IEXQ2:146# CHECK-NEXT: [9] - SiFiveP800IEXQ3:147# CHECK-NEXT: [10] - SiFiveP800IEXQ4:148# CHECK-NEXT: [11] - SiFiveP800IEXQ5:149# CHECK-NEXT: [12] - SiFiveP800IntArith:4 SiFiveP800IEXQ0, SiFiveP800IEXQ1, SiFiveP800IEXQ2, SiFiveP800IEXQ350# CHECK-NEXT: [13] - SiFiveP800LD:151# CHECK-NEXT: [14] - SiFiveP800LDST:252# CHECK-NEXT: [15] - SiFiveP800Load:3 SiFiveP800LDST, SiFiveP800LDST, SiFiveP800LD53# CHECK-NEXT: [16] - SiFiveP800Mul:2 SiFiveP800IEXQ1, SiFiveP800IEXQ354# CHECK-NEXT: [17] - SiFiveP800VDiv:155# CHECK-NEXT: [18] - SiFiveP800VEXQ0:156# CHECK-NEXT: [19] - SiFiveP800VEXQ1:157# CHECK-NEXT: [20] - SiFiveP800VFloatDiv:158# CHECK-NEXT: [21] - SiFiveP800VLD:159# CHECK-NEXT: [22] - SiFiveP800VST:160# CHECK-NEXT: [23] - SiFiveP800VectorArith:2 SiFiveP800VEXQ0, SiFiveP800VEXQ161 62# CHECK: Instruction Info:63# CHECK-NEXT: [1]: #uOps64# CHECK-NEXT: [2]: Latency65# CHECK-NEXT: [3]: RThroughput66# CHECK-NEXT: [4]: MayLoad67# CHECK-NEXT: [5]: MayStore68# CHECK-NEXT: [6]: HasSideEffects (U)69# CHECK-NEXT: [7]: Bypass Latency70# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])71# CHECK-NEXT: [9]: LLVM Opcode Name72 73# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:74# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, ta, ma75# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VMSLT_VV vmslt.vv v0, v4, v2076# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VMSLE_VV vmsle.vv v8, v4, v2077# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VMSLT_VV vmslt.vv v8, v4, v2078# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VMSLE_VV vmsle.vv v8, v4, v2079# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VMSEQ_VV vmseq.vv v8, v4, v2080# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VMSNE_VV vmsne.vv v8, v4, v2081# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VMSLTU_VV vmsltu.vv v8, v4, v2082# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VMSLEU_VV vmsleu.vv v8, v4, v2083# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VMSLTU_VV vmsltu.vv v8, v4, v2084# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VMSLEU_VV vmsleu.vv v8, v4, v2085# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VMFLT_VV vmflt.vv v0, v4, v2086# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VMFLE_VV vmfle.vv v8, v4, v2087# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VMFLT_VV vmflt.vv v8, v4, v2088# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VMFLE_VV vmfle.vv v8, v4, v2089# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VMFEQ_VV vmfeq.vv v8, v4, v2090# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VMFNE_VV vmfne.vv v8, v4, v2091# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VMADC_VV vmadc.vv v8, v4, v2092# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VMSBC_VV vmsbc.vv v8, v4, v2093# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VEXQ0,SiFiveP800VectorArith VFIRST_M vfirst.m a2, v494# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VEXQ0,SiFiveP800VectorArith VCPOP_M vcpop.m a2, v495# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VEXQ0,SiFiveP800VectorArith VIOTA_M viota.m v8, v496# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VEXQ0,SiFiveP800VectorArith VMSBF_M vmsbf.m v8, v497# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VEXQ0,SiFiveP800VectorArith VMSIF_M vmsif.m v8, v498# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VEXQ0,SiFiveP800VectorArith VMSOF_M vmsof.m v8, v499 100# CHECK: Resources:101# CHECK-NEXT: [0] - SiFiveP800Div102# CHECK-NEXT: [1] - SiFiveP800FEXQ0103# CHECK-NEXT: [2] - SiFiveP800FEXQ1104# CHECK-NEXT: [3] - SiFiveP800FloatDiv105# CHECK-NEXT: [4] - SiFiveP800IEXQ0106# CHECK-NEXT: [5] - SiFiveP800IEXQ1107# CHECK-NEXT: [6] - SiFiveP800IEXQ2108# CHECK-NEXT: [7] - SiFiveP800IEXQ3109# CHECK-NEXT: [8] - SiFiveP800IEXQ4110# CHECK-NEXT: [9] - SiFiveP800IEXQ5111# CHECK-NEXT: [10] - SiFiveP800LD112# CHECK-NEXT: [11.0] - SiFiveP800LDST113# CHECK-NEXT: [11.1] - SiFiveP800LDST114# CHECK-NEXT: [12] - SiFiveP800VDiv115# CHECK-NEXT: [13] - SiFiveP800VEXQ0116# CHECK-NEXT: [14] - SiFiveP800VEXQ1117# CHECK-NEXT: [15] - SiFiveP800VFloatDiv118# CHECK-NEXT: [16] - SiFiveP800VLD119# CHECK-NEXT: [17] - SiFiveP800VST120 121# CHECK: Resource pressure per iteration:122# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [12] [13] [14] [15] [16] [17]123# CHECK-NEXT: - - - - - 1.00 - - - - - - - - 15.00 9.00 - - -124 125# CHECK: Resource pressure by instruction:126# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [12] [13] [14] [15] [16] [17] Instructions:127# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma128# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vmslt.vv v0, v4, v20129# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vmsle.vv v8, v4, v20130# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vmslt.vv v8, v4, v20131# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vmsle.vv v8, v4, v20132# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vmseq.vv v8, v4, v20133# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vmsne.vv v8, v4, v20134# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vmsltu.vv v8, v4, v20135# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vmsleu.vv v8, v4, v20136# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vmsltu.vv v8, v4, v20137# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vmsleu.vv v8, v4, v20138# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vmflt.vv v0, v4, v20139# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vmfle.vv v8, v4, v20140# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vmflt.vv v8, v4, v20141# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vmfle.vv v8, v4, v20142# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vmfeq.vv v8, v4, v20143# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vmfne.vv v8, v4, v20144# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vmadc.vv v8, v4, v20145# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vmsbc.vv v8, v4, v20146# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - vfirst.m a2, v4147# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - vcpop.m a2, v4148# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - viota.m v8, v4149# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - vmsbf.m v8, v4150# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - vmsif.m v8, v4151# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - vmsof.m v8, v4152