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1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py2# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870 -iterations=1 -instruction-tables=full < %s | FileCheck %s3 4mul s6, s6, s75 6mulw s4, s4, a27 8cpop t1, t19 10cpopw t2, t211 12# CHECK: Resources:13# CHECK-NEXT: [0] - SiFiveP800Branch:2 SiFiveP800IEXQ4, SiFiveP800IEXQ514# CHECK-NEXT: [1] - SiFiveP800Div:115# CHECK-NEXT: [2] - SiFiveP800FEXQ0:116# CHECK-NEXT: [3] - SiFiveP800FEXQ1:117# CHECK-NEXT: [4] - SiFiveP800FloatArith:2 SiFiveP800FEXQ0, SiFiveP800FEXQ118# CHECK-NEXT: [5] - SiFiveP800FloatDiv:119# CHECK-NEXT: [6] - SiFiveP800IEXQ0:120# CHECK-NEXT: [7] - SiFiveP800IEXQ1:121# CHECK-NEXT: [8] - SiFiveP800IEXQ2:122# CHECK-NEXT: [9] - SiFiveP800IEXQ3:123# CHECK-NEXT: [10] - SiFiveP800IEXQ4:124# CHECK-NEXT: [11] - SiFiveP800IEXQ5:125# CHECK-NEXT: [12] - SiFiveP800IntArith:4 SiFiveP800IEXQ0, SiFiveP800IEXQ1, SiFiveP800IEXQ2, SiFiveP800IEXQ326# CHECK-NEXT: [13] - SiFiveP800LD:127# CHECK-NEXT: [14] - SiFiveP800LDST:228# CHECK-NEXT: [15] - SiFiveP800Load:3 SiFiveP800LDST, SiFiveP800LDST, SiFiveP800LD29# CHECK-NEXT: [16] - SiFiveP800Mul:2 SiFiveP800IEXQ1, SiFiveP800IEXQ330# CHECK-NEXT: [17] - SiFiveP800VDiv:131# CHECK-NEXT: [18] - SiFiveP800VEXQ0:132# CHECK-NEXT: [19] - SiFiveP800VEXQ1:133# CHECK-NEXT: [20] - SiFiveP800VFloatDiv:134# CHECK-NEXT: [21] - SiFiveP800VLD:135# CHECK-NEXT: [22] - SiFiveP800VST:136# CHECK-NEXT: [23] - SiFiveP800VectorArith:2 SiFiveP800VEXQ0, SiFiveP800VEXQ137 38# CHECK: Instruction Info:39# CHECK-NEXT: [1]: #uOps40# CHECK-NEXT: [2]: Latency41# CHECK-NEXT: [3]: RThroughput42# CHECK-NEXT: [4]: MayLoad43# CHECK-NEXT: [5]: MayStore44# CHECK-NEXT: [6]: HasSideEffects (U)45# CHECK-NEXT: [7]: Bypass Latency46# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])47# CHECK-NEXT: [9]: LLVM Opcode Name48 49# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:50# CHECK-NEXT: 1 2 0.50 2 SiFiveP800IntArith,SiFiveP800Mul MUL mul s6, s6, s751# CHECK-NEXT: 1 2 0.50 2 SiFiveP800IntArith,SiFiveP800Mul MULW mulw s4, s4, a252# CHECK-NEXT: 1 2 0.50 2 SiFiveP800IntArith,SiFiveP800Mul CPOP cpop t1, t153# CHECK-NEXT: 1 2 0.50 2 SiFiveP800IntArith,SiFiveP800Mul CPOPW cpopw t2, t254 55# CHECK: Resources:56# CHECK-NEXT: [0] - SiFiveP800Div57# CHECK-NEXT: [1] - SiFiveP800FEXQ058# CHECK-NEXT: [2] - SiFiveP800FEXQ159# CHECK-NEXT: [3] - SiFiveP800FloatDiv60# CHECK-NEXT: [4] - SiFiveP800IEXQ061# CHECK-NEXT: [5] - SiFiveP800IEXQ162# CHECK-NEXT: [6] - SiFiveP800IEXQ263# CHECK-NEXT: [7] - SiFiveP800IEXQ364# CHECK-NEXT: [8] - SiFiveP800IEXQ465# CHECK-NEXT: [9] - SiFiveP800IEXQ566# CHECK-NEXT: [10] - SiFiveP800LD67# CHECK-NEXT: [11.0] - SiFiveP800LDST68# CHECK-NEXT: [11.1] - SiFiveP800LDST69# CHECK-NEXT: [12] - SiFiveP800VDiv70# CHECK-NEXT: [13] - SiFiveP800VEXQ071# CHECK-NEXT: [14] - SiFiveP800VEXQ172# CHECK-NEXT: [15] - SiFiveP800VFloatDiv73# CHECK-NEXT: [16] - SiFiveP800VLD74# CHECK-NEXT: [17] - SiFiveP800VST75 76# CHECK: Resource pressure per iteration:77# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [12] [13] [14] [15] [16] [17]78# CHECK-NEXT: - - - - - 2.00 - 2.00 - - - - - - - - - - -79 80# CHECK: Resource pressure by instruction:81# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [12] [13] [14] [15] [16] [17] Instructions:82# CHECK-NEXT: - - - - - 0.50 - 0.50 - - - - - - - - - - - mul s6, s6, s783# CHECK-NEXT: - - - - - 0.50 - 0.50 - - - - - - - - - - - mulw s4, s4, a284# CHECK-NEXT: - - - - - 0.50 - 0.50 - - - - - - - - - - - cpop t1, t185# CHECK-NEXT: - - - - - 0.50 - 0.50 - - - - - - - - - - - cpopw t2, t286