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1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py2# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870 -iterations=1 -instruction-tables=full < %s | FileCheck %s3 4vsetvli zero, zero, e8, mf8, ta, ma5vlse8.v v8, (a0), t06vsetvli zero, zero, e8, mf4, ta, ma7vlse8.v v8, (a0), t08vsetvli zero, zero, e8, mf2, ta, ma9vlse8.v v8, (a0), t010vsetvli zero, zero, e8, m1, ta, ma11vlse8.v v8, (a0), t012vsetvli zero, zero, e8, m2, ta, ma13vlse8.v v8, (a0), t014vsetvli zero, zero, e8, m4, ta, ma15vlse8.v v8, (a0), t016vsetvli zero, zero, e8, m8, ta, ma17vlse8.v v8, (a0), t018 19vsetvli zero, zero, e16, mf4, ta, ma20vlse16.v v8, (a0), t021vsetvli zero, zero, e16, mf2, ta, ma22vlse16.v v8, (a0), t023vsetvli zero, zero, e16, m1, ta, ma24vlse16.v v8, (a0), t025vsetvli zero, zero, e16, m2, ta, ma26vlse16.v v8, (a0), t027vsetvli zero, zero, e16, m4, ta, ma28vlse16.v v8, (a0), t029vsetvli zero, zero, e16, m8, ta, ma30vlse16.v v8, (a0), t031 32vsetvli zero, zero, e32, mf2, ta, ma33vlse32.v v8, (a0), t034vsetvli zero, zero, e32, m1, ta, ma35vlse32.v v8, (a0), t036vsetvli zero, zero, e32, m2, ta, ma37vlse32.v v8, (a0), t038vsetvli zero, zero, e32, m4, ta, ma39vlse32.v v8, (a0), t040vsetvli zero, zero, e32, m8, ta, ma41vlse32.v v8, (a0), t042 43vsetvli zero, zero, e64, m1, ta, ma44vlse64.v v8, (a0), t045vsetvli zero, zero, e64, m2, ta, ma46vlse64.v v8, (a0), t047vsetvli zero, zero, e64, m4, ta, ma48vlse64.v v8, (a0), t049vsetvli zero, zero, e64, m8, ta, ma50vlse64.v v8, (a0), t051 52vsetvli zero, zero, e8, mf8, ta, ma53vsse8.v v8, (a0), t054vsetvli zero, zero, e8, mf4, ta, ma55vsse8.v v8, (a0), t056vsetvli zero, zero, e8, mf2, ta, ma57vsse8.v v8, (a0), t058vsetvli zero, zero, e8, m1, ta, ma59vsse8.v v8, (a0), t060vsetvli zero, zero, e8, m2, ta, ma61vsse8.v v8, (a0), t062vsetvli zero, zero, e8, m4, ta, ma63vsse8.v v8, (a0), t064vsetvli zero, zero, e8, m8, ta, ma65vsse8.v v8, (a0), t066 67vsetvli zero, zero, e16, mf4, ta, ma68vsse16.v v8, (a0), t069vsetvli zero, zero, e16, mf2, ta, ma70vsse16.v v8, (a0), t071vsetvli zero, zero, e16, m1, ta, ma72vsse16.v v8, (a0), t073vsetvli zero, zero, e16, m2, ta, ma74vsse16.v v8, (a0), t075vsetvli zero, zero, e16, m4, ta, ma76vsse16.v v8, (a0), t077vsetvli zero, zero, e16, m8, ta, ma78vsse16.v v8, (a0), t079 80vsetvli zero, zero, e32, mf2, ta, ma81vsse32.v v8, (a0), t082vsetvli zero, zero, e32, m1, ta, ma83vsse32.v v8, (a0), t084vsetvli zero, zero, e32, m2, ta, ma85vsse32.v v8, (a0), t086vsetvli zero, zero, e32, m4, ta, ma87vsse32.v v8, (a0), t088vsetvli zero, zero, e32, m8, ta, ma89vsse32.v v8, (a0), t090 91vsetvli zero, zero, e64, m1, ta, ma92vsse64.v v8, (a0), t093vsetvli zero, zero, e64, m2, ta, ma94vsse64.v v8, (a0), t095vsetvli zero, zero, e64, m4, ta, ma96vsse64.v v8, (a0), t097vsetvli zero, zero, e64, m8, ta, ma98vsse64.v v8, (a0), t099 100# CHECK: Resources:101# CHECK-NEXT: [0] - SiFiveP800Branch:2 SiFiveP800IEXQ4, SiFiveP800IEXQ5102# CHECK-NEXT: [1] - SiFiveP800Div:1103# CHECK-NEXT: [2] - SiFiveP800FEXQ0:1104# CHECK-NEXT: [3] - SiFiveP800FEXQ1:1105# CHECK-NEXT: [4] - SiFiveP800FloatArith:2 SiFiveP800FEXQ0, SiFiveP800FEXQ1106# CHECK-NEXT: [5] - SiFiveP800FloatDiv:1107# CHECK-NEXT: [6] - SiFiveP800IEXQ0:1108# CHECK-NEXT: [7] - SiFiveP800IEXQ1:1109# CHECK-NEXT: [8] - SiFiveP800IEXQ2:1110# CHECK-NEXT: [9] - SiFiveP800IEXQ3:1111# CHECK-NEXT: [10] - SiFiveP800IEXQ4:1112# CHECK-NEXT: [11] - SiFiveP800IEXQ5:1113# CHECK-NEXT: [12] - SiFiveP800IntArith:4 SiFiveP800IEXQ0, SiFiveP800IEXQ1, SiFiveP800IEXQ2, SiFiveP800IEXQ3114# CHECK-NEXT: [13] - SiFiveP800LD:1115# CHECK-NEXT: [14] - SiFiveP800LDST:2116# CHECK-NEXT: [15] - SiFiveP800Load:3 SiFiveP800LDST, SiFiveP800LDST, SiFiveP800LD117# CHECK-NEXT: [16] - SiFiveP800Mul:2 SiFiveP800IEXQ1, SiFiveP800IEXQ3118# CHECK-NEXT: [17] - SiFiveP800VDiv:1119# CHECK-NEXT: [18] - SiFiveP800VEXQ0:1120# CHECK-NEXT: [19] - SiFiveP800VEXQ1:1121# CHECK-NEXT: [20] - SiFiveP800VFloatDiv:1122# CHECK-NEXT: [21] - SiFiveP800VLD:1123# CHECK-NEXT: [22] - SiFiveP800VST:1124# CHECK-NEXT: [23] - SiFiveP800VectorArith:2 SiFiveP800VEXQ0, SiFiveP800VEXQ1125 126# CHECK: Instruction Info:127# CHECK-NEXT: [1]: #uOps128# CHECK-NEXT: [2]: Latency129# CHECK-NEXT: [3]: RThroughput130# CHECK-NEXT: [4]: MayLoad131# CHECK-NEXT: [5]: MayStore132# CHECK-NEXT: [6]: HasSideEffects (U)133# CHECK-NEXT: [7]: Bypass Latency134# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])135# CHECK-NEXT: [9]: LLVM Opcode Name136 137# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:138# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, ta, ma139# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VLD VLSE8_V vlse8.v v8, (a0), t0140# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, ta, ma141# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VLD VLSE8_V vlse8.v v8, (a0), t0142# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, ta, ma143# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VLD VLSE8_V vlse8.v v8, (a0), t0144# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, ta, ma145# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VLD VLSE8_V vlse8.v v8, (a0), t0146# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m2, ta, ma147# CHECK-NEXT: 1 12 2.00 * 12 SiFiveP800VLD[2] VLSE8_V vlse8.v v8, (a0), t0148# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m4, ta, ma149# CHECK-NEXT: 1 12 4.00 * 12 SiFiveP800VLD[4] VLSE8_V vlse8.v v8, (a0), t0150# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m8, ta, ma151# CHECK-NEXT: 1 12 8.00 * 12 SiFiveP800VLD[8] VLSE8_V vlse8.v v8, (a0), t0152# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, ta, ma153# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VLD VLSE16_V vlse16.v v8, (a0), t0154# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, ta, ma155# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VLD VLSE16_V vlse16.v v8, (a0), t0156# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, ta, ma157# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VLD VLSE16_V vlse16.v v8, (a0), t0158# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m2, ta, ma159# CHECK-NEXT: 1 12 2.00 * 12 SiFiveP800VLD[2] VLSE16_V vlse16.v v8, (a0), t0160# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m4, ta, ma161# CHECK-NEXT: 1 12 4.00 * 12 SiFiveP800VLD[4] VLSE16_V vlse16.v v8, (a0), t0162# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m8, ta, ma163# CHECK-NEXT: 1 12 8.00 * 12 SiFiveP800VLD[8] VLSE16_V vlse16.v v8, (a0), t0164# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, ta, ma165# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VLD VLSE32_V vlse32.v v8, (a0), t0166# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, ta, ma167# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VLD VLSE32_V vlse32.v v8, (a0), t0168# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m2, ta, ma169# CHECK-NEXT: 1 12 2.00 * 12 SiFiveP800VLD[2] VLSE32_V vlse32.v v8, (a0), t0170# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m4, ta, ma171# CHECK-NEXT: 1 12 4.00 * 12 SiFiveP800VLD[4] VLSE32_V vlse32.v v8, (a0), t0172# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m8, ta, ma173# CHECK-NEXT: 1 12 8.00 * 12 SiFiveP800VLD[8] VLSE32_V vlse32.v v8, (a0), t0174# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, ta, ma175# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VLD VLSE64_V vlse64.v v8, (a0), t0176# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m2, ta, ma177# CHECK-NEXT: 1 12 2.00 * 12 SiFiveP800VLD[2] VLSE64_V vlse64.v v8, (a0), t0178# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m4, ta, ma179# CHECK-NEXT: 1 12 4.00 * 12 SiFiveP800VLD[4] VLSE64_V vlse64.v v8, (a0), t0180# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m8, ta, ma181# CHECK-NEXT: 1 12 8.00 * 12 SiFiveP800VLD[8] VLSE64_V vlse64.v v8, (a0), t0182# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, ta, ma183# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VST VSSE8_V vsse8.v v8, (a0), t0184# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, ta, ma185# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VST VSSE8_V vsse8.v v8, (a0), t0186# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, ta, ma187# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VST VSSE8_V vsse8.v v8, (a0), t0188# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, ta, ma189# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VST VSSE8_V vsse8.v v8, (a0), t0190# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m2, ta, ma191# CHECK-NEXT: 1 12 2.00 * 12 SiFiveP800VST[2] VSSE8_V vsse8.v v8, (a0), t0192# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m4, ta, ma193# CHECK-NEXT: 1 12 4.00 * 12 SiFiveP800VST[4] VSSE8_V vsse8.v v8, (a0), t0194# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m8, ta, ma195# CHECK-NEXT: 1 12 8.00 * 12 SiFiveP800VST[8] VSSE8_V vsse8.v v8, (a0), t0196# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, ta, ma197# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VST VSSE16_V vsse16.v v8, (a0), t0198# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, ta, ma199# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VST VSSE16_V vsse16.v v8, (a0), t0200# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, ta, ma201# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VST VSSE16_V vsse16.v v8, (a0), t0202# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m2, ta, ma203# CHECK-NEXT: 1 12 2.00 * 12 SiFiveP800VST[2] VSSE16_V vsse16.v v8, (a0), t0204# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m4, ta, ma205# CHECK-NEXT: 1 12 4.00 * 12 SiFiveP800VST[4] VSSE16_V vsse16.v v8, (a0), t0206# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m8, ta, ma207# CHECK-NEXT: 1 12 8.00 * 12 SiFiveP800VST[8] VSSE16_V vsse16.v v8, (a0), t0208# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, ta, ma209# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VST VSSE32_V vsse32.v v8, (a0), t0210# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, ta, ma211# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VST VSSE32_V vsse32.v v8, (a0), t0212# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m2, ta, ma213# CHECK-NEXT: 1 12 2.00 * 12 SiFiveP800VST[2] VSSE32_V vsse32.v v8, (a0), t0214# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m4, ta, ma215# CHECK-NEXT: 1 12 4.00 * 12 SiFiveP800VST[4] VSSE32_V vsse32.v v8, (a0), t0216# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m8, ta, ma217# CHECK-NEXT: 1 12 8.00 * 12 SiFiveP800VST[8] VSSE32_V vsse32.v v8, (a0), t0218# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, ta, ma219# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VST VSSE64_V vsse64.v v8, (a0), t0220# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m2, ta, ma221# CHECK-NEXT: 1 12 2.00 * 12 SiFiveP800VST[2] VSSE64_V vsse64.v v8, (a0), t0222# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m4, ta, ma223# CHECK-NEXT: 1 12 4.00 * 12 SiFiveP800VST[4] VSSE64_V vsse64.v v8, (a0), t0224# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m8, ta, ma225# CHECK-NEXT: 1 12 8.00 * 12 SiFiveP800VST[8] VSSE64_V vsse64.v v8, (a0), t0226 227# CHECK: Resources:228# CHECK-NEXT: [0] - SiFiveP800Div229# CHECK-NEXT: [1] - SiFiveP800FEXQ0230# CHECK-NEXT: [2] - SiFiveP800FEXQ1231# CHECK-NEXT: [3] - SiFiveP800FloatDiv232# CHECK-NEXT: [4] - SiFiveP800IEXQ0233# CHECK-NEXT: [5] - SiFiveP800IEXQ1234# CHECK-NEXT: [6] - SiFiveP800IEXQ2235# CHECK-NEXT: [7] - SiFiveP800IEXQ3236# CHECK-NEXT: [8] - SiFiveP800IEXQ4237# CHECK-NEXT: [9] - SiFiveP800IEXQ5238# CHECK-NEXT: [10] - SiFiveP800LD239# CHECK-NEXT: [11.0] - SiFiveP800LDST240# CHECK-NEXT: [11.1] - SiFiveP800LDST241# CHECK-NEXT: [12] - SiFiveP800VDiv242# CHECK-NEXT: [13] - SiFiveP800VEXQ0243# CHECK-NEXT: [14] - SiFiveP800VEXQ1244# CHECK-NEXT: [15] - SiFiveP800VFloatDiv245# CHECK-NEXT: [16] - SiFiveP800VLD246# CHECK-NEXT: [17] - SiFiveP800VST247 248# CHECK: Resource pressure per iteration:249# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [12] [13] [14] [15] [16] [17]250# CHECK-NEXT: - - - - - 44.00 - - - - - - - - - - - 66.00 66.00251 252# CHECK: Resource pressure by instruction:253# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [12] [13] [14] [15] [16] [17] Instructions:254# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma255# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - vlse8.v v8, (a0), t0256# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma257# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - vlse8.v v8, (a0), t0258# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma259# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - vlse8.v v8, (a0), t0260# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma261# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - vlse8.v v8, (a0), t0262# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma263# CHECK-NEXT: - - - - - - - - - - - - - - - - - 2.00 - vlse8.v v8, (a0), t0264# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma265# CHECK-NEXT: - - - - - - - - - - - - - - - - - 4.00 - vlse8.v v8, (a0), t0266# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma267# CHECK-NEXT: - - - - - - - - - - - - - - - - - 8.00 - vlse8.v v8, (a0), t0268# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma269# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - vlse16.v v8, (a0), t0270# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma271# CHECK-NEXT: - - - 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CHECK-NEXT: - - - - - - - - - - - - - - - - - - 8.00 vsse64.v v8, (a0), t0342