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1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py2# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870 -iterations=1 -instruction-tables=full < %s | FileCheck %s3 4# These instructions only work with e645 6vsetvli zero, zero, e64, m1, tu, mu7vclmul.vv v4, v8, v128vclmul.vx v4, v8, a09vclmulh.vv v4, v8, v1210vclmulh.vx v4, v8, a011 12vsetvli zero, zero, e64, m2, tu, mu13vclmul.vv v4, v8, v1214vclmul.vx v4, v8, a015vclmulh.vv v4, v8, v1216vclmulh.vx v4, v8, a017 18vsetvli zero, zero, e64, m4, tu, mu19vclmul.vv v4, v8, v1220vclmul.vx v4, v8, a021vclmulh.vv v4, v8, v1222vclmulh.vx v4, v8, a023 24vsetvli zero, zero, e64, m8, tu, mu25vclmul.vv v8, v12, v2426vclmul.vx v8, v12, a027vclmulh.vv v8, v12, v2428vclmulh.vx v8, v12, a029 30# CHECK: Resources:31# CHECK-NEXT: [0] - SiFiveP800Branch:2 SiFiveP800IEXQ4, SiFiveP800IEXQ532# CHECK-NEXT: [1] - SiFiveP800Div:133# CHECK-NEXT: [2] - SiFiveP800FEXQ0:134# CHECK-NEXT: [3] - SiFiveP800FEXQ1:135# CHECK-NEXT: [4] - SiFiveP800FloatArith:2 SiFiveP800FEXQ0, SiFiveP800FEXQ136# CHECK-NEXT: [5] - SiFiveP800FloatDiv:137# CHECK-NEXT: [6] - SiFiveP800IEXQ0:138# CHECK-NEXT: [7] - SiFiveP800IEXQ1:139# CHECK-NEXT: [8] - SiFiveP800IEXQ2:140# CHECK-NEXT: [9] - SiFiveP800IEXQ3:141# CHECK-NEXT: [10] - SiFiveP800IEXQ4:142# CHECK-NEXT: [11] - SiFiveP800IEXQ5:143# CHECK-NEXT: [12] - SiFiveP800IntArith:4 SiFiveP800IEXQ0, SiFiveP800IEXQ1, SiFiveP800IEXQ2, SiFiveP800IEXQ344# CHECK-NEXT: [13] - SiFiveP800LD:145# CHECK-NEXT: [14] - SiFiveP800LDST:246# CHECK-NEXT: [15] - SiFiveP800Load:3 SiFiveP800LDST, SiFiveP800LDST, SiFiveP800LD47# CHECK-NEXT: [16] - SiFiveP800Mul:2 SiFiveP800IEXQ1, SiFiveP800IEXQ348# CHECK-NEXT: [17] - SiFiveP800VDiv:149# CHECK-NEXT: [18] - SiFiveP800VEXQ0:150# CHECK-NEXT: [19] - SiFiveP800VEXQ1:151# CHECK-NEXT: [20] - SiFiveP800VFloatDiv:152# CHECK-NEXT: [21] - SiFiveP800VLD:153# CHECK-NEXT: [22] - SiFiveP800VST:154# CHECK-NEXT: [23] - SiFiveP800VectorArith:2 SiFiveP800VEXQ0, SiFiveP800VEXQ155 56# CHECK: Instruction Info:57# CHECK-NEXT: [1]: #uOps58# CHECK-NEXT: [2]: Latency59# CHECK-NEXT: [3]: RThroughput60# CHECK-NEXT: [4]: MayLoad61# CHECK-NEXT: [5]: MayStore62# CHECK-NEXT: [6]: HasSideEffects (U)63# CHECK-NEXT: [7]: Bypass Latency64# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])65# CHECK-NEXT: [9]: LLVM Opcode Name66 67# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:68# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu69# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VCLMUL_VV vclmul.vv v4, v8, v1270# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VCLMUL_VX vclmul.vx v4, v8, a071# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VCLMULH_VV vclmulh.vv v4, v8, v1272# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VCLMULH_VX vclmulh.vx v4, v8, a073# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m2, tu, mu74# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VCLMUL_VV vclmul.vv v4, v8, v1275# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VCLMUL_VX vclmul.vx v4, v8, a076# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VCLMULH_VV vclmulh.vv v4, v8, v1277# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VCLMULH_VX vclmulh.vx v4, v8, a078# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m4, tu, mu79# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VCLMUL_VV vclmul.vv v4, v8, v1280# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VCLMUL_VX vclmul.vx v4, v8, a081# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VCLMULH_VV vclmulh.vv v4, v8, v1282# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VCLMULH_VX vclmulh.vx v4, v8, a083# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m8, tu, mu84# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VCLMUL_VV vclmul.vv v8, v12, v2485# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VCLMUL_VX vclmul.vx v8, v12, a086# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VCLMULH_VV vclmulh.vv v8, v12, v2487# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VCLMULH_VX vclmulh.vx v8, v12, a088 89# CHECK: Resources:90# CHECK-NEXT: [0] - SiFiveP800Div91# CHECK-NEXT: [1] - SiFiveP800FEXQ092# CHECK-NEXT: [2] - SiFiveP800FEXQ193# CHECK-NEXT: [3] - SiFiveP800FloatDiv94# CHECK-NEXT: [4] - SiFiveP800IEXQ095# CHECK-NEXT: [5] - SiFiveP800IEXQ196# CHECK-NEXT: [6] - SiFiveP800IEXQ297# CHECK-NEXT: [7] - SiFiveP800IEXQ398# CHECK-NEXT: [8] - SiFiveP800IEXQ499# CHECK-NEXT: [9] - SiFiveP800IEXQ5100# CHECK-NEXT: [10] - SiFiveP800LD101# CHECK-NEXT: [11.0] - SiFiveP800LDST102# CHECK-NEXT: [11.1] - SiFiveP800LDST103# CHECK-NEXT: [12] - SiFiveP800VDiv104# CHECK-NEXT: [13] - SiFiveP800VEXQ0105# CHECK-NEXT: [14] - SiFiveP800VEXQ1106# CHECK-NEXT: [15] - SiFiveP800VFloatDiv107# CHECK-NEXT: [16] - SiFiveP800VLD108# CHECK-NEXT: [17] - SiFiveP800VST109 110# CHECK: Resource pressure per iteration:111# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [12] [13] [14] [15] [16] [17]112# CHECK-NEXT: - - - - - 4.00 - - - - - - - - 30.00 30.00 - - -113 114# CHECK: Resource pressure by instruction:115# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [12] [13] [14] [15] [16] [17] Instructions:116# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu117# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vclmul.vv v4, v8, v12118# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vclmul.vx v4, v8, a0119# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vclmulh.vv v4, v8, v12120# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vclmulh.vx v4, v8, a0121# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu122# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vclmul.vv v4, v8, v12123# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vclmul.vx v4, v8, a0124# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vclmulh.vv v4, v8, v12125# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vclmulh.vx v4, v8, a0126# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu127# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vclmul.vv v4, v8, v12128# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vclmul.vx v4, v8, a0129# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vclmulh.vv v4, v8, v12130# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vclmulh.vx v4, v8, a0131# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m8, tu, mu132# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vclmul.vv v8, v12, v24133# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vclmul.vx v8, v12, a0134# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vclmulh.vv v8, v12, v24135# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vclmulh.vx v8, v12, a0136