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1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py2# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870 -iterations=1 -instruction-tables=full < %s | FileCheck %s3 4vsetvli zero, zero, e8, mf8, tu, mu5vghsh.vv v4, v8, v126vgmul.vv v4, v87 8vsetvli zero, zero, e16, mf4, tu, mu9vghsh.vv v4, v8, v1210vgmul.vv v4, v811 12vsetvli zero, zero, e32, mf2, tu, mu13vghsh.vv v4, v8, v1214vgmul.vv v4, v815 16vsetvli zero, zero, e32, m1, tu, mu17vghsh.vv v4, v8, v1218vgmul.vv v4, v819 20vsetvli zero, zero, e32, m2, tu, mu21vghsh.vv v4, v8, v1222vgmul.vv v4, v823 24vsetvli zero, zero, e32, m4, tu, mu25vghsh.vv v4, v8, v1226vgmul.vv v4, v827 28vsetvli zero, zero, e32, m8, tu, mu29vghsh.vv v8, v16, v2430vgmul.vv v8, v1631 32# Show SEW does not matter33vsetvli zero, zero, e64, m4, tu, mu34vghsh.vv v4, v8, v1235vgmul.vv v4, v836 37# CHECK: Resources:38# CHECK-NEXT: [0] - SiFiveP800Branch:2 SiFiveP800IEXQ4, SiFiveP800IEXQ539# CHECK-NEXT: [1] - SiFiveP800Div:140# CHECK-NEXT: [2] - SiFiveP800FEXQ0:141# CHECK-NEXT: [3] - SiFiveP800FEXQ1:142# CHECK-NEXT: [4] - SiFiveP800FloatArith:2 SiFiveP800FEXQ0, SiFiveP800FEXQ143# CHECK-NEXT: [5] - SiFiveP800FloatDiv:144# CHECK-NEXT: [6] - SiFiveP800IEXQ0:145# CHECK-NEXT: [7] - SiFiveP800IEXQ1:146# CHECK-NEXT: [8] - SiFiveP800IEXQ2:147# CHECK-NEXT: [9] - SiFiveP800IEXQ3:148# CHECK-NEXT: [10] - SiFiveP800IEXQ4:149# CHECK-NEXT: [11] - SiFiveP800IEXQ5:150# CHECK-NEXT: [12] - SiFiveP800IntArith:4 SiFiveP800IEXQ0, SiFiveP800IEXQ1, SiFiveP800IEXQ2, SiFiveP800IEXQ351# CHECK-NEXT: [13] - SiFiveP800LD:152# CHECK-NEXT: [14] - SiFiveP800LDST:253# CHECK-NEXT: [15] - SiFiveP800Load:3 SiFiveP800LDST, SiFiveP800LDST, SiFiveP800LD54# CHECK-NEXT: [16] - SiFiveP800Mul:2 SiFiveP800IEXQ1, SiFiveP800IEXQ355# CHECK-NEXT: [17] - SiFiveP800VDiv:156# CHECK-NEXT: [18] - SiFiveP800VEXQ0:157# CHECK-NEXT: [19] - SiFiveP800VEXQ1:158# CHECK-NEXT: [20] - SiFiveP800VFloatDiv:159# CHECK-NEXT: [21] - SiFiveP800VLD:160# CHECK-NEXT: [22] - SiFiveP800VST:161# CHECK-NEXT: [23] - SiFiveP800VectorArith:2 SiFiveP800VEXQ0, SiFiveP800VEXQ162 63# CHECK: Instruction Info:64# CHECK-NEXT: [1]: #uOps65# CHECK-NEXT: [2]: Latency66# CHECK-NEXT: [3]: RThroughput67# CHECK-NEXT: [4]: MayLoad68# CHECK-NEXT: [5]: MayStore69# CHECK-NEXT: [6]: HasSideEffects (U)70# CHECK-NEXT: [7]: Bypass Latency71# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])72# CHECK-NEXT: [9]: LLVM Opcode Name73 74# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:75# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu76# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VGHSH_VV vghsh.vv v4, v8, v1277# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VGMUL_VV vgmul.vv v4, v878# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu79# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VGHSH_VV vghsh.vv v4, v8, v1280# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VGMUL_VV vgmul.vv v4, v881# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu82# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VGHSH_VV vghsh.vv v4, v8, v1283# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VGMUL_VV vgmul.vv v4, v884# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu85# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VGHSH_VV vghsh.vv v4, v8, v1286# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VGMUL_VV vgmul.vv v4, v887# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m2, tu, mu88# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VGHSH_VV vghsh.vv v4, v8, v1289# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VGMUL_VV vgmul.vv v4, v890# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m4, tu, mu91# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VGHSH_VV vghsh.vv v4, v8, v1292# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VGMUL_VV vgmul.vv v4, v893# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m8, tu, mu94# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VGHSH_VV vghsh.vv v8, v16, v2495# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VGMUL_VV vgmul.vv v8, v1696# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m4, tu, mu97# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VGHSH_VV vghsh.vv v4, v8, v1298# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VGMUL_VV vgmul.vv v4, v899 100# CHECK: Resources:101# CHECK-NEXT: [0] - SiFiveP800Div102# CHECK-NEXT: [1] - SiFiveP800FEXQ0103# CHECK-NEXT: [2] - SiFiveP800FEXQ1104# CHECK-NEXT: [3] - SiFiveP800FloatDiv105# CHECK-NEXT: [4] - SiFiveP800IEXQ0106# CHECK-NEXT: [5] - SiFiveP800IEXQ1107# CHECK-NEXT: [6] - SiFiveP800IEXQ2108# CHECK-NEXT: [7] - SiFiveP800IEXQ3109# CHECK-NEXT: [8] - SiFiveP800IEXQ4110# CHECK-NEXT: [9] - SiFiveP800IEXQ5111# CHECK-NEXT: [10] - SiFiveP800LD112# CHECK-NEXT: [11.0] - SiFiveP800LDST113# CHECK-NEXT: [11.1] - SiFiveP800LDST114# CHECK-NEXT: [12] - SiFiveP800VDiv115# CHECK-NEXT: [13] - SiFiveP800VEXQ0116# CHECK-NEXT: [14] - SiFiveP800VEXQ1117# CHECK-NEXT: [15] - SiFiveP800VFloatDiv118# CHECK-NEXT: [16] - SiFiveP800VLD119# CHECK-NEXT: [17] - SiFiveP800VST120 121# CHECK: Resource pressure per iteration:122# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [12] [13] [14] [15] [16] [17]123# CHECK-NEXT: - - - - - 8.00 - - - - - - - - 36.00 36.00 - - -124 125# CHECK: Resource pressure by instruction:126# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [12] [13] [14] [15] [16] [17] Instructions:127# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu128# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vghsh.vv v4, v8, v12129# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vgmul.vv v4, v8130# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu131# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vghsh.vv v4, v8, v12132# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vgmul.vv v4, v8133# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu134# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vghsh.vv v4, v8, v12135# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vgmul.vv v4, v8136# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu137# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vghsh.vv v4, v8, v12138# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vgmul.vv v4, v8139# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu140# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vghsh.vv v4, v8, v12141# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vgmul.vv v4, v8142# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu143# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vghsh.vv v4, v8, v12144# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vgmul.vv v4, v8145# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu146# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vghsh.vv v8, v16, v24147# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vgmul.vv v8, v16148# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu149# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vghsh.vv v4, v8, v12150# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vgmul.vv v4, v8151