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1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py2# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870 -iterations=1 -instruction-tables=full < %s | FileCheck %s3 4# These instructions only support e325 6vsetvli zero, zero, e32, mf2, tu, mu7vaesef.vv v4, v88vaesef.vs v4, v89vaesem.vv v4, v810vaesem.vs v4, v811vaesdm.vv v4, v812vaesdm.vs v4, v813vaeskf1.vi v4, v8, 814vaeskf2.vi v4, v8, 815vaesz.vs v4, v816 17vsetvli zero, zero, e32, m1, tu, mu18vaesef.vv v4, v819vaesef.vs v4, v820vaesem.vv v4, v821vaesem.vs v4, v822vaesdm.vv v4, v823vaesdm.vs v4, v824vaeskf1.vi v4, v8, 825vaeskf2.vi v4, v8, 826vaesz.vs v4, v827 28vsetvli zero, zero, e32, m2, tu, mu29vaesef.vv v4, v830vaesef.vs v4, v831vaesem.vv v4, v832vaesem.vs v4, v833vaesdm.vv v4, v834vaesdm.vs v4, v835vaeskf1.vi v4, v8, 836vaeskf2.vi v4, v8, 837vaesz.vs v4, v838 39vsetvli zero, zero, e32, m4, tu, mu40vaesef.vv v4, v841vaesef.vs v4, v842vaesem.vv v4, v843vaesem.vs v4, v844vaesdm.vv v4, v845vaesdm.vs v4, v846vaeskf1.vi v4, v8, 847vaeskf2.vi v4, v8, 848vaesz.vs v4, v849 50vsetvli zero, zero, e32, m8, tu, mu51vaesef.vv v8, v1652vaesef.vs v8, v1653vaesem.vv v8, v1654vaesem.vs v8, v1655vaesdm.vv v8, v1656vaesdm.vs v8, v1657vaeskf1.vi v8, v16, 858vaeskf2.vi v8, v16, 859vaesz.vs v8, v1660 61# CHECK: Resources:62# CHECK-NEXT: [0] - SiFiveP800Branch:2 SiFiveP800IEXQ4, SiFiveP800IEXQ563# CHECK-NEXT: [1] - SiFiveP800Div:164# CHECK-NEXT: [2] - SiFiveP800FEXQ0:165# CHECK-NEXT: [3] - SiFiveP800FEXQ1:166# CHECK-NEXT: [4] - SiFiveP800FloatArith:2 SiFiveP800FEXQ0, SiFiveP800FEXQ167# CHECK-NEXT: [5] - SiFiveP800FloatDiv:168# CHECK-NEXT: [6] - SiFiveP800IEXQ0:169# CHECK-NEXT: [7] - SiFiveP800IEXQ1:170# CHECK-NEXT: [8] - SiFiveP800IEXQ2:171# CHECK-NEXT: [9] - SiFiveP800IEXQ3:172# CHECK-NEXT: [10] - SiFiveP800IEXQ4:173# CHECK-NEXT: [11] - SiFiveP800IEXQ5:174# CHECK-NEXT: [12] - SiFiveP800IntArith:4 SiFiveP800IEXQ0, SiFiveP800IEXQ1, SiFiveP800IEXQ2, SiFiveP800IEXQ375# CHECK-NEXT: [13] - SiFiveP800LD:176# CHECK-NEXT: [14] - SiFiveP800LDST:277# CHECK-NEXT: [15] - SiFiveP800Load:3 SiFiveP800LDST, SiFiveP800LDST, SiFiveP800LD78# CHECK-NEXT: [16] - SiFiveP800Mul:2 SiFiveP800IEXQ1, SiFiveP800IEXQ379# CHECK-NEXT: [17] - SiFiveP800VDiv:180# CHECK-NEXT: [18] - SiFiveP800VEXQ0:181# CHECK-NEXT: [19] - SiFiveP800VEXQ1:182# CHECK-NEXT: [20] - SiFiveP800VFloatDiv:183# CHECK-NEXT: [21] - SiFiveP800VLD:184# CHECK-NEXT: [22] - SiFiveP800VST:185# CHECK-NEXT: [23] - SiFiveP800VectorArith:2 SiFiveP800VEXQ0, SiFiveP800VEXQ186 87# CHECK: Instruction Info:88# CHECK-NEXT: [1]: #uOps89# CHECK-NEXT: [2]: Latency90# CHECK-NEXT: [3]: RThroughput91# CHECK-NEXT: [4]: MayLoad92# CHECK-NEXT: [5]: MayStore93# CHECK-NEXT: [6]: HasSideEffects (U)94# CHECK-NEXT: [7]: Bypass Latency95# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])96# CHECK-NEXT: [9]: LLVM Opcode Name97 98# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:99# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu100# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VAESEF_VV vaesef.vv v4, v8101# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VAESEF_VS vaesef.vs v4, v8102# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VAESEM_VV vaesem.vv v4, v8103# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VAESEM_VS vaesem.vs v4, v8104# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VAESDM_VV vaesdm.vv v4, v8105# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VAESDM_VS vaesdm.vs v4, v8106# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VAESKF1_VI vaeskf1.vi v4, v8, 8107# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VAESKF2_VI vaeskf2.vi v4, v8, 8108# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VAESZ_VS vaesz.vs v4, v8109# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu110# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VAESEF_VV vaesef.vv v4, v8111# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VAESEF_VS vaesef.vs v4, v8112# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VAESEM_VV vaesem.vv v4, v8113# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VAESEM_VS vaesem.vs v4, v8114# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VAESDM_VV vaesdm.vv v4, v8115# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VAESDM_VS vaesdm.vs v4, v8116# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VAESKF1_VI vaeskf1.vi v4, v8, 8117# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VAESKF2_VI vaeskf2.vi v4, v8, 8118# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VAESZ_VS vaesz.vs v4, v8119# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m2, tu, mu120# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VAESEF_VV vaesef.vv v4, v8121# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VAESEF_VS vaesef.vs v4, v8122# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VAESEM_VV vaesem.vv v4, v8123# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VAESEM_VS vaesem.vs v4, v8124# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VAESDM_VV vaesdm.vv v4, v8125# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VAESDM_VS vaesdm.vs v4, v8126# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VAESKF1_VI vaeskf1.vi v4, v8, 8127# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VAESKF2_VI vaeskf2.vi v4, v8, 8128# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VAESZ_VS vaesz.vs v4, v8129# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m4, tu, mu130# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VAESEF_VV vaesef.vv v4, v8131# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VAESEF_VS vaesef.vs v4, v8132# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VAESEM_VV vaesem.vv v4, v8133# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VAESEM_VS vaesem.vs v4, v8134# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VAESDM_VV vaesdm.vv v4, v8135# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VAESDM_VS vaesdm.vs v4, v8136# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VAESKF1_VI vaeskf1.vi v4, v8, 8137# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VAESKF2_VI vaeskf2.vi v4, v8, 8138# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VAESZ_VS vaesz.vs v4, v8139# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m8, tu, mu140# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VAESEF_VV vaesef.vv v8, v16141# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VAESEF_VS vaesef.vs v8, v16142# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VAESEM_VV vaesem.vv v8, v16143# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VAESEM_VS vaesem.vs v8, v16144# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VAESDM_VV vaesdm.vv v8, v16145# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VAESDM_VS vaesdm.vs v8, v16146# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VAESKF1_VI vaeskf1.vi v8, v16, 8147# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VAESKF2_VI vaeskf2.vi v8, v16, 8148# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VAESZ_VS vaesz.vs v8, v16149 150# CHECK: Resources:151# CHECK-NEXT: [0] - SiFiveP800Div152# CHECK-NEXT: [1] - SiFiveP800FEXQ0153# CHECK-NEXT: [2] - SiFiveP800FEXQ1154# CHECK-NEXT: [3] - SiFiveP800FloatDiv155# CHECK-NEXT: [4] - SiFiveP800IEXQ0156# CHECK-NEXT: [5] - SiFiveP800IEXQ1157# CHECK-NEXT: [6] - SiFiveP800IEXQ2158# CHECK-NEXT: [7] - SiFiveP800IEXQ3159# CHECK-NEXT: [8] - SiFiveP800IEXQ4160# CHECK-NEXT: [9] - SiFiveP800IEXQ5161# CHECK-NEXT: [10] - SiFiveP800LD162# CHECK-NEXT: [11.0] - SiFiveP800LDST163# CHECK-NEXT: [11.1] - SiFiveP800LDST164# CHECK-NEXT: [12] - SiFiveP800VDiv165# CHECK-NEXT: [13] - SiFiveP800VEXQ0166# CHECK-NEXT: [14] - SiFiveP800VEXQ1167# CHECK-NEXT: [15] - SiFiveP800VFloatDiv168# CHECK-NEXT: [16] - SiFiveP800VLD169# CHECK-NEXT: [17] - SiFiveP800VST170 171# CHECK: Resource pressure per iteration:172# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [12] [13] [14] [15] [16] [17]173# CHECK-NEXT: - - - - - 5.00 - - - - - - - - 72.00 72.00 - - -174 175# CHECK: Resource pressure by instruction:176# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [12] [13] [14] [15] [16] [17] Instructions:177# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu178# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vaesef.vv v4, v8179# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vaesef.vs v4, v8180# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vaesem.vv v4, v8181# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vaesem.vs v4, v8182# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vaesdm.vv v4, v8183# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vaesdm.vs v4, v8184# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vaeskf1.vi v4, v8, 8185# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vaeskf2.vi v4, v8, 8186# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vaesz.vs v4, v8187# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu188# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vaesef.vv v4, v8189# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vaesef.vs v4, v8190# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vaesem.vv v4, v8191# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vaesem.vs v4, v8192# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vaesdm.vv v4, v8193# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vaesdm.vs v4, v8194# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vaeskf1.vi v4, v8, 8195# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vaeskf2.vi v4, v8, 8196# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vaesz.vs v4, v8197# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu198# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vaesef.vv v4, v8199# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vaesef.vs v4, v8200# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vaesem.vv v4, v8201# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vaesem.vs v4, v8202# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vaesdm.vv v4, v8203# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vaesdm.vs v4, v8204# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vaeskf1.vi v4, v8, 8205# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vaeskf2.vi v4, v8, 8206# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vaesz.vs v4, v8207# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu208# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vaesef.vv v4, v8209# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vaesef.vs v4, v8210# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vaesem.vv v4, v8211# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vaesem.vs v4, v8212# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vaesdm.vv v4, v8213# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vaesdm.vs v4, v8214# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vaeskf1.vi v4, v8, 8215# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vaeskf2.vi v4, v8, 8216# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vaesz.vs v4, v8217# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu218# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vaesef.vv v8, v16219# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vaesef.vs v8, v16220# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vaesem.vv v8, v16221# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vaesem.vs v8, v16222# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vaesdm.vv v8, v16223# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vaesdm.vs v8, v16224# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vaeskf1.vi v8, v16, 8225# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vaeskf2.vi v8, v16, 8226# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vaesz.vs v8, v16227