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1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py2# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870 -iterations=1 -instruction-tables=full < %s | FileCheck %s3 4# Worst case for vsha2ms should be that of LMUL=8 and SEW=64.5vsha2ms.vv v4, v8, v126 7# SEW is only e32 or e648 9vsetvli zero, zero, e32, m1, tu, mu10vsha2ms.vv v4, v8, v1211vsha2ch.vv v4, v8, v1212vsha2cl.vv v4, v8, v1213 14vsetvli zero, zero, e32, m2, tu, mu15vsha2ms.vv v4, v8, v1216vsha2ch.vv v4, v8, v1217vsha2cl.vv v4, v8, v1218 19vsetvli zero, zero, e32, m4, tu, mu20vsha2ms.vv v4, v8, v1221vsha2ch.vv v4, v8, v1222vsha2cl.vv v4, v8, v1223 24vsetvli zero, zero, e32, m8, tu, mu25vsha2ms.vv v8, v16, v2426vsha2ch.vv v8, v16, v2427vsha2cl.vv v8, v16, v2428 29vsetvli zero, zero, e64, m1, tu, mu30vsha2ms.vv v4, v8, v1231vsha2ch.vv v4, v8, v1232vsha2cl.vv v4, v8, v1233 34vsetvli zero, zero, e64, m2, tu, mu35vsha2ms.vv v4, v8, v1236vsha2ch.vv v4, v8, v1237vsha2cl.vv v4, v8, v1238 39vsetvli zero, zero, e64, m4, tu, mu40vsha2ms.vv v4, v8, v1241vsha2ch.vv v4, v8, v1242vsha2cl.vv v4, v8, v1243 44vsetvli zero, zero, e64, m8, tu, mu45vsha2ms.vv v8, v16, v2446vsha2ch.vv v8, v16, v2447vsha2cl.vv v8, v16, v2448 49# CHECK: Resources:50# CHECK-NEXT: [0] - SiFiveP800Branch:2 SiFiveP800IEXQ4, SiFiveP800IEXQ551# CHECK-NEXT: [1] - SiFiveP800Div:152# CHECK-NEXT: [2] - SiFiveP800FEXQ0:153# CHECK-NEXT: [3] - SiFiveP800FEXQ1:154# CHECK-NEXT: [4] - SiFiveP800FloatArith:2 SiFiveP800FEXQ0, SiFiveP800FEXQ155# CHECK-NEXT: [5] - SiFiveP800FloatDiv:156# CHECK-NEXT: [6] - SiFiveP800IEXQ0:157# CHECK-NEXT: [7] - SiFiveP800IEXQ1:158# CHECK-NEXT: [8] - SiFiveP800IEXQ2:159# CHECK-NEXT: [9] - SiFiveP800IEXQ3:160# CHECK-NEXT: [10] - SiFiveP800IEXQ4:161# CHECK-NEXT: [11] - SiFiveP800IEXQ5:162# CHECK-NEXT: [12] - SiFiveP800IntArith:4 SiFiveP800IEXQ0, SiFiveP800IEXQ1, SiFiveP800IEXQ2, SiFiveP800IEXQ363# CHECK-NEXT: [13] - SiFiveP800LD:164# CHECK-NEXT: [14] - SiFiveP800LDST:265# CHECK-NEXT: [15] - SiFiveP800Load:3 SiFiveP800LDST, SiFiveP800LDST, SiFiveP800LD66# CHECK-NEXT: [16] - SiFiveP800Mul:2 SiFiveP800IEXQ1, SiFiveP800IEXQ367# CHECK-NEXT: [17] - SiFiveP800VDiv:168# CHECK-NEXT: [18] - SiFiveP800VEXQ0:169# CHECK-NEXT: [19] - SiFiveP800VEXQ1:170# CHECK-NEXT: [20] - SiFiveP800VFloatDiv:171# CHECK-NEXT: [21] - SiFiveP800VLD:172# CHECK-NEXT: [22] - SiFiveP800VST:173# CHECK-NEXT: [23] - SiFiveP800VectorArith:2 SiFiveP800VEXQ0, SiFiveP800VEXQ174 75# CHECK: Instruction Info:76# CHECK-NEXT: [1]: #uOps77# CHECK-NEXT: [2]: Latency78# CHECK-NEXT: [3]: RThroughput79# CHECK-NEXT: [4]: MayLoad80# CHECK-NEXT: [5]: MayStore81# CHECK-NEXT: [6]: HasSideEffects (U)82# CHECK-NEXT: [7]: Bypass Latency83# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])84# CHECK-NEXT: [9]: LLVM Opcode Name85 86# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:87# CHECK-NEXT: 1 3 8.00 3 SiFiveP800VEXQ0[8],SiFiveP800VectorArith[8] VSHA2MS_VV vsha2ms.vv v4, v8, v1288# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu89# CHECK-NEXT: 1 3 1.00 3 SiFiveP800VEXQ0,SiFiveP800VectorArith VSHA2MS_VV vsha2ms.vv v4, v8, v1290# CHECK-NEXT: 1 3 1.00 3 SiFiveP800VEXQ0,SiFiveP800VectorArith VSHA2CH_VV vsha2ch.vv v4, v8, v1291# CHECK-NEXT: 1 3 1.00 3 SiFiveP800VEXQ0,SiFiveP800VectorArith VSHA2CL_VV vsha2cl.vv v4, v8, v1292# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m2, tu, mu93# CHECK-NEXT: 1 3 2.00 3 SiFiveP800VEXQ0[2],SiFiveP800VectorArith[2] VSHA2MS_VV vsha2ms.vv v4, v8, v1294# CHECK-NEXT: 1 3 2.00 3 SiFiveP800VEXQ0[2],SiFiveP800VectorArith[2] VSHA2CH_VV vsha2ch.vv v4, v8, v1295# CHECK-NEXT: 1 3 2.00 3 SiFiveP800VEXQ0[2],SiFiveP800VectorArith[2] VSHA2CL_VV vsha2cl.vv v4, v8, v1296# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m4, tu, mu97# CHECK-NEXT: 1 3 4.00 3 SiFiveP800VEXQ0[4],SiFiveP800VectorArith[4] VSHA2MS_VV vsha2ms.vv v4, v8, v1298# CHECK-NEXT: 1 3 4.00 3 SiFiveP800VEXQ0[4],SiFiveP800VectorArith[4] VSHA2CH_VV vsha2ch.vv v4, v8, v1299# CHECK-NEXT: 1 3 4.00 3 SiFiveP800VEXQ0[4],SiFiveP800VectorArith[4] VSHA2CL_VV vsha2cl.vv v4, v8, v12100# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m8, tu, mu101# CHECK-NEXT: 1 3 8.00 3 SiFiveP800VEXQ0[8],SiFiveP800VectorArith[8] VSHA2MS_VV vsha2ms.vv v8, v16, v24102# CHECK-NEXT: 1 3 8.00 3 SiFiveP800VEXQ0[8],SiFiveP800VectorArith[8] VSHA2CH_VV vsha2ch.vv v8, v16, v24103# CHECK-NEXT: 1 3 8.00 3 SiFiveP800VEXQ0[8],SiFiveP800VectorArith[8] VSHA2CL_VV vsha2cl.vv v8, v16, v24104# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu105# CHECK-NEXT: 1 3 1.00 3 SiFiveP800VEXQ0,SiFiveP800VectorArith VSHA2MS_VV vsha2ms.vv v4, v8, v12106# CHECK-NEXT: 1 3 1.00 3 SiFiveP800VEXQ0,SiFiveP800VectorArith VSHA2CH_VV vsha2ch.vv v4, v8, v12107# CHECK-NEXT: 1 3 1.00 3 SiFiveP800VEXQ0,SiFiveP800VectorArith VSHA2CL_VV vsha2cl.vv v4, v8, v12108# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m2, tu, mu109# CHECK-NEXT: 1 3 2.00 3 SiFiveP800VEXQ0[2],SiFiveP800VectorArith[2] VSHA2MS_VV vsha2ms.vv v4, v8, v12110# CHECK-NEXT: 1 3 2.00 3 SiFiveP800VEXQ0[2],SiFiveP800VectorArith[2] VSHA2CH_VV vsha2ch.vv v4, v8, v12111# CHECK-NEXT: 1 3 2.00 3 SiFiveP800VEXQ0[2],SiFiveP800VectorArith[2] VSHA2CL_VV vsha2cl.vv v4, v8, v12112# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m4, tu, mu113# CHECK-NEXT: 1 3 4.00 3 SiFiveP800VEXQ0[4],SiFiveP800VectorArith[4] VSHA2MS_VV vsha2ms.vv v4, v8, v12114# CHECK-NEXT: 1 3 4.00 3 SiFiveP800VEXQ0[4],SiFiveP800VectorArith[4] VSHA2CH_VV vsha2ch.vv v4, v8, v12115# CHECK-NEXT: 1 3 4.00 3 SiFiveP800VEXQ0[4],SiFiveP800VectorArith[4] VSHA2CL_VV vsha2cl.vv v4, v8, v12116# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m8, tu, mu117# CHECK-NEXT: 1 3 8.00 3 SiFiveP800VEXQ0[8],SiFiveP800VectorArith[8] VSHA2MS_VV vsha2ms.vv v8, v16, v24118# CHECK-NEXT: 1 3 8.00 3 SiFiveP800VEXQ0[8],SiFiveP800VectorArith[8] VSHA2CH_VV vsha2ch.vv v8, v16, v24119# CHECK-NEXT: 1 3 8.00 3 SiFiveP800VEXQ0[8],SiFiveP800VectorArith[8] VSHA2CL_VV vsha2cl.vv v8, v16, v24120 121# CHECK: Resources:122# CHECK-NEXT: [0] - SiFiveP800Div123# CHECK-NEXT: [1] - SiFiveP800FEXQ0124# CHECK-NEXT: [2] - SiFiveP800FEXQ1125# CHECK-NEXT: [3] - SiFiveP800FloatDiv126# CHECK-NEXT: [4] - SiFiveP800IEXQ0127# CHECK-NEXT: [5] - SiFiveP800IEXQ1128# CHECK-NEXT: [6] - SiFiveP800IEXQ2129# CHECK-NEXT: [7] - SiFiveP800IEXQ3130# CHECK-NEXT: [8] - SiFiveP800IEXQ4131# CHECK-NEXT: [9] - SiFiveP800IEXQ5132# CHECK-NEXT: [10] - SiFiveP800LD133# CHECK-NEXT: [11.0] - SiFiveP800LDST134# CHECK-NEXT: [11.1] - SiFiveP800LDST135# CHECK-NEXT: [12] - SiFiveP800VDiv136# CHECK-NEXT: [13] - SiFiveP800VEXQ0137# CHECK-NEXT: [14] - SiFiveP800VEXQ1138# CHECK-NEXT: [15] - SiFiveP800VFloatDiv139# CHECK-NEXT: [16] - SiFiveP800VLD140# CHECK-NEXT: [17] - SiFiveP800VST141 142# CHECK: Resource pressure per iteration:143# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [12] [13] [14] [15] [16] [17]144# CHECK-NEXT: - - - - - 8.00 - - - - - - - - 98.00 - - - -145 146# CHECK: Resource pressure by instruction:147# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [12] [13] [14] [15] [16] [17] Instructions:148# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - - - vsha2ms.vv v4, v8, v12149# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu150# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - vsha2ms.vv v4, v8, v12151# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - vsha2ch.vv v4, v8, v12152# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - vsha2cl.vv v4, v8, v12153# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu154# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - - - vsha2ms.vv v4, v8, v12155# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - - - vsha2ch.vv v4, v8, v12156# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - - - vsha2cl.vv v4, v8, v12157# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu158# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - - - vsha2ms.vv v4, v8, v12159# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - - - vsha2ch.vv v4, v8, v12160# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - - - vsha2cl.vv v4, v8, v12161# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu162# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - - - vsha2ms.vv v8, v16, v24163# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - - - vsha2ch.vv v8, v16, v24164# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - - - vsha2cl.vv v8, v16, v24165# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu166# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - vsha2ms.vv v4, v8, v12167# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - vsha2ch.vv v4, v8, v12168# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - vsha2cl.vv v4, v8, v12169# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu170# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - - - vsha2ms.vv v4, v8, v12171# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - - - vsha2ch.vv v4, v8, v12172# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - - - vsha2cl.vv v4, v8, v12173# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu174# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - - - vsha2ms.vv v4, v8, v12175# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - - - vsha2ch.vv v4, v8, v12176# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - - - vsha2cl.vv v4, v8, v12177# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m8, tu, mu178# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - - - vsha2ms.vv v8, v16, v24179# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - - - vsha2ch.vv v8, v16, v24180# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - - - vsha2cl.vv v8, v16, v24181