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1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py2# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870 -iterations=1 -instruction-tables=full < %s | FileCheck %s3 4# These instructions only support e325 6vsetvli zero, zero, e32, mf2, tu, mu7vsm4k.vi v4, v8, 88vsm4r.vv v4, v89vsm4r.vs v4, v810 11vsetvli zero, zero, e32, m1, tu, mu12vsm4k.vi v4, v8, 813vsm4r.vv v4, v814vsm4r.vs v4, v815 16vsetvli zero, zero, e32, m2, tu, mu17vsm4k.vi v4, v8, 818vsm4r.vv v4, v819vsm4r.vs v4, v820 21vsetvli zero, zero, e32, m4, tu, mu22vsm4k.vi v4, v8, 823vsm4r.vv v4, v824vsm4r.vs v4, v825 26vsetvli zero, zero, e32, m8, tu, mu27vsm4k.vi v8, v16, 828vsm4r.vv v8, v1629vsm4r.vs v8, v1630 31# CHECK: Resources:32# CHECK-NEXT: [0] - SiFiveP800Branch:2 SiFiveP800IEXQ4, SiFiveP800IEXQ533# CHECK-NEXT: [1] - SiFiveP800Div:134# CHECK-NEXT: [2] - SiFiveP800FEXQ0:135# CHECK-NEXT: [3] - SiFiveP800FEXQ1:136# CHECK-NEXT: [4] - SiFiveP800FloatArith:2 SiFiveP800FEXQ0, SiFiveP800FEXQ137# CHECK-NEXT: [5] - SiFiveP800FloatDiv:138# CHECK-NEXT: [6] - SiFiveP800IEXQ0:139# CHECK-NEXT: [7] - SiFiveP800IEXQ1:140# CHECK-NEXT: [8] - SiFiveP800IEXQ2:141# CHECK-NEXT: [9] - SiFiveP800IEXQ3:142# CHECK-NEXT: [10] - SiFiveP800IEXQ4:143# CHECK-NEXT: [11] - SiFiveP800IEXQ5:144# CHECK-NEXT: [12] - SiFiveP800IntArith:4 SiFiveP800IEXQ0, SiFiveP800IEXQ1, SiFiveP800IEXQ2, SiFiveP800IEXQ345# CHECK-NEXT: [13] - SiFiveP800LD:146# CHECK-NEXT: [14] - SiFiveP800LDST:247# CHECK-NEXT: [15] - SiFiveP800Load:3 SiFiveP800LDST, SiFiveP800LDST, SiFiveP800LD48# CHECK-NEXT: [16] - SiFiveP800Mul:2 SiFiveP800IEXQ1, SiFiveP800IEXQ349# CHECK-NEXT: [17] - SiFiveP800VDiv:150# CHECK-NEXT: [18] - SiFiveP800VEXQ0:151# CHECK-NEXT: [19] - SiFiveP800VEXQ1:152# CHECK-NEXT: [20] - SiFiveP800VFloatDiv:153# CHECK-NEXT: [21] - SiFiveP800VLD:154# CHECK-NEXT: [22] - SiFiveP800VST:155# CHECK-NEXT: [23] - SiFiveP800VectorArith:2 SiFiveP800VEXQ0, SiFiveP800VEXQ156 57# CHECK: Instruction Info:58# CHECK-NEXT: [1]: #uOps59# CHECK-NEXT: [2]: Latency60# CHECK-NEXT: [3]: RThroughput61# CHECK-NEXT: [4]: MayLoad62# CHECK-NEXT: [5]: MayStore63# CHECK-NEXT: [6]: HasSideEffects (U)64# CHECK-NEXT: [7]: Bypass Latency65# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])66# CHECK-NEXT: [9]: LLVM Opcode Name67 68# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:69# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu70# CHECK-NEXT: 1 3 1.00 3 SiFiveP800VEXQ0,SiFiveP800VectorArith VSM4K_VI vsm4k.vi v4, v8, 871# CHECK-NEXT: 1 3 1.00 3 SiFiveP800VEXQ0,SiFiveP800VectorArith VSM4R_VV vsm4r.vv v4, v872# CHECK-NEXT: 1 3 1.00 3 SiFiveP800VEXQ0,SiFiveP800VectorArith VSM4R_VS vsm4r.vs v4, v873# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu74# CHECK-NEXT: 1 3 1.00 3 SiFiveP800VEXQ0,SiFiveP800VectorArith VSM4K_VI vsm4k.vi v4, v8, 875# CHECK-NEXT: 1 3 1.00 3 SiFiveP800VEXQ0,SiFiveP800VectorArith VSM4R_VV vsm4r.vv v4, v876# CHECK-NEXT: 1 3 1.00 3 SiFiveP800VEXQ0,SiFiveP800VectorArith VSM4R_VS vsm4r.vs v4, v877# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m2, tu, mu78# CHECK-NEXT: 1 3 2.00 3 SiFiveP800VEXQ0[2],SiFiveP800VectorArith[2] VSM4K_VI vsm4k.vi v4, v8, 879# CHECK-NEXT: 1 3 2.00 3 SiFiveP800VEXQ0[2],SiFiveP800VectorArith[2] VSM4R_VV vsm4r.vv v4, v880# CHECK-NEXT: 1 3 2.00 3 SiFiveP800VEXQ0[2],SiFiveP800VectorArith[2] VSM4R_VS vsm4r.vs v4, v881# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m4, tu, mu82# CHECK-NEXT: 1 3 4.00 3 SiFiveP800VEXQ0[4],SiFiveP800VectorArith[4] VSM4K_VI vsm4k.vi v4, v8, 883# CHECK-NEXT: 1 3 4.00 3 SiFiveP800VEXQ0[4],SiFiveP800VectorArith[4] VSM4R_VV vsm4r.vv v4, v884# CHECK-NEXT: 1 3 4.00 3 SiFiveP800VEXQ0[4],SiFiveP800VectorArith[4] VSM4R_VS vsm4r.vs v4, v885# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m8, tu, mu86# CHECK-NEXT: 1 3 8.00 3 SiFiveP800VEXQ0[8],SiFiveP800VectorArith[8] VSM4K_VI vsm4k.vi v8, v16, 887# CHECK-NEXT: 1 3 8.00 3 SiFiveP800VEXQ0[8],SiFiveP800VectorArith[8] VSM4R_VV vsm4r.vv v8, v1688# CHECK-NEXT: 1 3 8.00 3 SiFiveP800VEXQ0[8],SiFiveP800VectorArith[8] VSM4R_VS vsm4r.vs v8, v1689 90# CHECK: Resources:91# CHECK-NEXT: [0] - SiFiveP800Div92# CHECK-NEXT: [1] - SiFiveP800FEXQ093# CHECK-NEXT: [2] - SiFiveP800FEXQ194# CHECK-NEXT: [3] - SiFiveP800FloatDiv95# CHECK-NEXT: [4] - SiFiveP800IEXQ096# CHECK-NEXT: [5] - SiFiveP800IEXQ197# CHECK-NEXT: [6] - SiFiveP800IEXQ298# CHECK-NEXT: [7] - SiFiveP800IEXQ399# CHECK-NEXT: [8] - SiFiveP800IEXQ4100# CHECK-NEXT: [9] - SiFiveP800IEXQ5101# CHECK-NEXT: [10] - SiFiveP800LD102# CHECK-NEXT: [11.0] - SiFiveP800LDST103# CHECK-NEXT: [11.1] - SiFiveP800LDST104# CHECK-NEXT: [12] - SiFiveP800VDiv105# CHECK-NEXT: [13] - SiFiveP800VEXQ0106# CHECK-NEXT: [14] - SiFiveP800VEXQ1107# CHECK-NEXT: [15] - SiFiveP800VFloatDiv108# CHECK-NEXT: [16] - SiFiveP800VLD109# CHECK-NEXT: [17] - SiFiveP800VST110 111# CHECK: Resource pressure per iteration:112# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [12] [13] [14] [15] [16] [17]113# CHECK-NEXT: - - - - - 5.00 - - - - - - - - 48.00 - - - -114 115# CHECK: Resource pressure by instruction:116# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [12] [13] [14] [15] [16] [17] Instructions:117# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu118# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - vsm4k.vi v4, v8, 8119# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - vsm4r.vv v4, v8120# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - vsm4r.vs v4, v8121# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu122# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - vsm4k.vi v4, v8, 8123# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - vsm4r.vv v4, v8124# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - vsm4r.vs v4, v8125# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu126# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - - - vsm4k.vi v4, v8, 8127# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - - - vsm4r.vv v4, v8128# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - - - vsm4r.vs v4, v8129# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu130# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - - - vsm4k.vi v4, v8, 8131# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - - - vsm4r.vv v4, v8132# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - - - vsm4r.vs v4, v8133# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu134# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - - - vsm4k.vi v8, v16, 8135# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - - - vsm4r.vv v8, v16136# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - - - vsm4r.vs v8, v16137