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1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py2# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s3 4vsetvli zero, a0, e8, m1, tu, mu5# LLVM-MCA-RISCV-LMUL M16vadd.vv v12, v12, v127vsetvli zero, a0, e8, m8, tu, mu8# LLVM-MCA-RISCV-LMUL M89vadd.vv v12, v12, v1210 11# CHECK: Iterations: 112# CHECK-NEXT: Instructions: 413# CHECK-NEXT: Total Cycles: 1214# CHECK-NEXT: Total uOps: 415 16# CHECK: Dispatch Width: 217# CHECK-NEXT: uOps Per Cycle: 0.3318# CHECK-NEXT: IPC: 0.3319# CHECK-NEXT: Block RThroughput: 20.020 21# CHECK: Instruction Info:22# CHECK-NEXT: [1]: #uOps23# CHECK-NEXT: [2]: Latency24# CHECK-NEXT: [3]: RThroughput25# CHECK-NEXT: [4]: MayLoad26# CHECK-NEXT: [5]: MayStore27# CHECK-NEXT: [6]: HasSideEffects (U)28 29# CHECK: [1] [2] [3] [4] [5] [6] Instructions:30# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu31# CHECK-NEXT: 1 4 2.00 vadd.vv v12, v12, v1232# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m8, tu, mu33# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v1234 35# CHECK: Resources:36# CHECK-NEXT: [0] - VLEN512SiFive7FDiv37# CHECK-NEXT: [1] - VLEN512SiFive7IDiv38# CHECK-NEXT: [2] - VLEN512SiFive7PipeA39# CHECK-NEXT: [3] - VLEN512SiFive7PipeB40# CHECK-NEXT: [4] - VLEN512SiFive7VA41# CHECK-NEXT: [5] - VLEN512SiFive7VCQ42# CHECK-NEXT: [6] - VLEN512SiFive7VL43# CHECK-NEXT: [7] - VLEN512SiFive7VS44 45# CHECK: Resource pressure per iteration:46# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]47# CHECK-NEXT: - - 2.00 - 20.00 2.00 - -48 49# CHECK: Resource pressure by instruction:50# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:51# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu52# CHECK-NEXT: - - - - 3.00 1.00 - - vadd.vv v12, v12, v1253# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m8, tu, mu54# CHECK-NEXT: - - - - 17.00 1.00 - - vadd.vv v12, v12, v1255 56# CHECK: Timeline view:57# CHECK-NEXT: 0158# CHECK-NEXT: Index 012345678959 60# CHECK: [0,0] DeeE . .. vsetvli zero, a0, e8, m1, tu, mu61# CHECK-NEXT: [0,1] . DeeeE .. vadd.vv v12, v12, v1262# CHECK-NEXT: [0,2] . DeeE .. vsetvli zero, a0, e8, m8, tu, mu63# CHECK-NEXT: [0,3] . . DeeeE vadd.vv v12, v12, v1264 65# CHECK: Average Wait times (based on the timeline view):66# CHECK-NEXT: [0]: Executions67# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue68# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready69# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage70 71# CHECK: [0] [1] [2] [3]72# CHECK-NEXT: 0. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m1, tu, mu73# CHECK-NEXT: 1. 1 0.0 0.0 0.0 vadd.vv v12, v12, v1274# CHECK-NEXT: 2. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m8, tu, mu75# CHECK-NEXT: 3. 1 0.0 0.0 0.0 vadd.vv v12, v12, v1276# CHECK-NEXT: 1 0.0 0.0 0.0 <total>77